Dual mode thin film transistor liquid crystal display source driver circuit

• US 20020063674A1
• Filed: 11/27/2001
• Published: 05/30/2002
• Est. Priority Date: 11/30/2000
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chiang, Johnson
• Granted Patent: US 6,747,626 B2
• Time in Patent Office: Days
• US Class Current: 345/98
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

The present invention relates to a source driver circuit (200) for driving a thin film transistor liquid crystal display (TFT-LCD) panel. The source driver circuit (200) provides several different operating modes for the driver to lower the power consumption of a TFT-LCD module while still providing a wide analog voltage range to the liquid crystal display elements. A mode signal (MODE) switches the driver from gray scale to standby mode wherein the internal resistive digital to analog converter (202), decoder/output voltage drivers (210) and output buffer amplifiers (212) are powered down. In addition, only the most significant bit of data corresponding to red, green and blue are transferred to a sample and hold register (206, 208). Output cells (216), substituting for the decoder/output voltage drivers, receive one-bit data from hold registers (208) and provide voltage at the output of the driver circuit (200).

Claims

1. A source driver circuit for driving an LCD panel having reference voltages, comprising:

a shift register having a plurality of N addressable channels;

a plurality of data inputs connected to the source driver circuit for receiving input data indicative of an image to be displayed on the LCD, the input data being at a first digital input voltage level;

a plurality of sample registers coupled to the shift register, each sample register coupled to a corresponding one of the plurality of data inputs to receive the input data;

a plurality of hold registers, each hold register coupled to a corresponding one of the plurality of sample registers to receive the sampled input data, the plurality of hold registers coupled to receive a transfer signal wherein the transfer signal determines the timing for the transfer of sampled input data from each sample register to each respective hold register;

an internal resistive digital to analog circuit to produce linear voltage levels between any pair of adjacent reference voltages

a plurality of decoder cells, each decoder cell coupled to the internal resistive digital to analog circuit and each respective hold register such that each decoder cell is programmable to decode the input data to select respective output voltage levels;

a plurality of output cells coupled to receive a mode signal to activate each output cell, each output cell coupled to receive the held input data from each respective hold register;

a plurality of switches coupled to receive a mode signal to activate each switch, each switch connected to each of the decoder cells for switching between a first and second mode of operation wherein, in the first mode, when each switch is closed, the output cells are bypassed and, in the second mode, when each switch is open, the decoder cells are bypassed.

a plurality of driver outputs coupled to the plurality of output cells and the plurality of switches to receive each respective output voltage level for providing drive voltages derived from said input data to the LCD panel.

2. The source driver circuit as recited in claim 1, further comprising:

a plurality of latch circuits coupled to receive the mode signal, each latch circuit coupled to each respective hold register for providing programmable level of the data held in each respective hold register to each respective decoder cell when in the second mode of operation,

wherein, in the second mode of operation, one bit of input data is transferred to each respective output cell.

3. The source driver circuit as recited in claim 1, further comprising:

a plurality of latch circuits coupled to receive the mode signal, each latch circuit coupled to each respective sample register for providing programmable level of the data to each respective hold register when in the second mode of operation,

wherein, in the second mode of operation, one bit of input data is transferred to each respective hold register and one bit of input data is transferred to each respective output cell.