Low substrate-noise electrostatic discharge protection circuits with bi-directional silicon diodes

• US 20020064007A1
• Filed: 10/11/2001
• Published: 05/30/2002
• Est. Priority Date: 12/28/2000
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Chang, Chyh-Yih, Ker, Ming-Dou
• Granted Patent: US 6,617,649 B2
• Time in Patent Office: Days
• US Class Current: 361/56
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: Y10S 977/723 On an electrically insulating substrate

Abstract

An integrated circuit device that includes a plurality of electrostatic discharge clamp circuits, variously coupled to VDD, VSS and transistor, having at least one bi-directional silicon diode that includes a first silicon diode and a second silicon diode, wherein an n-type portion of the first silicon diode is coupled to a p-type portion of the second silicon diode and a p-type portion of the first silicon diode is coupled to an n-type portion of the second silicon diode, responsive to either a positive electrostatic discharge or a negative electrostatic discharge to provide electrostatic discharge protection.

Claims

1. An electrostatic discharge protection circuit, comprising:

at least one bi-directional silicon diode having a first silicon diode and a second silicon diode, wherein an n-type portion of the first silicon diode is coupled to a p-type portion of the second silicon diode and a p-type portion of the first silicon diode is coupled to an n-type portion of the second silicon diode, and

wherein the at least one bi-directional silicon diode is responsive to one of a positive electrostatic discharge or a negative electrostatic discharge.

2. The circuit as claimed in claim 1, wherein the at least one bi-directional silicon diode includes one or more serially coupled bi-directional silicon diodes.

3. The circuit as claimed in claim 1, wherein the first silicon diode includes a center silicon portion disposed between and contiguous with the p-type and n-type silicon portions of the first silicon diode.

4. The circuit as claimed in claim 1, wherein the second silicon diode includes a center silicon portion disposed between and contiguous with the p-type and n-type silicon portions of the second silicon diode.

5. The circuit as claimed in claim 1 further comprising,

a first isolation structure, and

a second isolation structure spaced apart from the first isolation structure,

wherein the p-type silicon portion of the first silicon diode overlaps the first isolation structure and the n-type silicon portion of the first silicon diode overlaps the second isolation structure.

6. The circuit as claimed in claim 5, further comprising a diffused region inside a well region adjacent one of the first isolation structure and second isolation structure, wherein the diffused region is doped with a same impurity as the well region.

7. The circuit as claimed in claim 1 further comprising,

a third isolation structure, and

a fourth isolation structure spaced apart from the third isolation structure,

wherein the p-type silicon portion of the second silicon diode overlaps the third isolation structure and the n-type silicon portion of the second silicon diode overlaps the fourth isolation structure.

8. The circuit as claimed in claim 7, further comprising a diffused region inside a well region adjacent one of the third isolation structure and fourth isolation structure, wherein the diffused region is doped with a same impurity as the well region.

9. The circuit as claimed in claim 1, wherein the first silicon diode includes n serially coupled silicon diodes and the second silicon diode includes m serially coupled silicon diodes, and wherein n and m are integers between 1 and infinity.

10. The circuit as claimed in claim 9, whereinndoes not equal to m.

28. The circuit as claimed in claim 1 further comprising,

a first voltage source, and

a second voltage source,

wherein the first voltage source is coupled to one end and the second voltage source is coupled to another end of the at least one bi-direction silicon diode, and

wherein the first voltage source is VDD and the second voltage source is VSS.

11. An electrostatic discharge protection circuit, comprising:

at least one bi-directional silicon diode having a first silicon-on-insulator diode and a second silicon-on-insulator diode, wherein an n-type portion of the first silicon-on-insulator diode is coupled to a p-type portion of the second silicon-on-insulator diode and a p-type portion of the first silicon-on-insulator diode is coupled to an n-type portion of the second silicon-on-insulator diode, and

wherein the at least one bi-directional silicon diode is responsive to one of a positive electrostatic discharge or a negative electrostatic discharge.

12. The circuit as claimed in claim 11, wherein the at least one bi-directional silicon diode includes one or more serially coupled bi-directional silicon diodes.

14. The circuit as claimed in claim 13, wherein the at least one bi-directional silicon diode includes one or more serially coupled bi-directional silicon diodes.

15. The circuit as claimed in claim 13, wherein the first voltage source is VDD, and the first electrostatic discharge clamp circuit is coupled to the signal pad to protect the circuit from at least a human body model, charged device model or machine model electrostatic discharge.

16. The circuit as claimed in claim 15, further comprising,

a second electrostatic discharge clamp circuit having at least one bi-directional silicon diode including a third silicon diode and a fourth silicon diode,

wherein an n-type portion of the third silicon diode is coupled to a p-type portion of the fourth silicon diode and a p-type portion of the third silicon diode is coupled to an n-type portion of the fourth silicon diode, and

wherein the second electrostatic discharge clamp circuit is coupled to VDD and a bulk of a first transistor at one end and to a gate of the first transistor at another end to protect the first transistor from at least a charged device model electrostatic discharge.

17. The circuit as claimed in claim 13, wherein the first voltage source is VSS, and the first electrostatic discharge clamp circuit is coupled to the signal pad to protect the circuit from at least a human body model electrostatic discharge or machine model electrostatic discharge.

18. The circuit as claimed in claim 17, further comprising,

a second electrostatic discharge clamp circuit having at least one bi-directional silicon diode including a third silicon diode and a fourth silicon diode,

wherein an n-type portion of the third silicon diode is coupled to a p-type portion of the fourth silicon diode and a p-type portion of the third silicon diode is coupled to an n-type portion of the fourth silicon diode, and

wherein the second electrostatic discharge clamp circuit is coupled to VDD at one end and the signal pad and the first electrostatic discharge clamp circuit at another end.

19. The circuit as claimed in claim 13, wherein the first voltage source is VDD, and the first electrostatic discharge clamp circuit is coupled to a bulk at one end and to a gate at another end of a first transistor to protect the first transistor from at least a charged device model electrostatic discharge.

20. The circuit as claimed in claim 19, further comprising,

a second electrostatic discharge clamp circuit having at least one bi-directional silicon diode including a third silicon diode and a fourth silicon diode,

wherein an n-type portion of the third silicon diode is coupled to a p-type portion of the fourth silicon diode and a p-type portion of the third silicon diode is coupled to an n-type portion of the fourth silicon diode, and

wherein the second electrostatic discharge clamp circuit is coupled to VDD at one end and the signal pad at another end to protect the circuit from at least a human body model electrostatic discharge or machine model electrostatic discharge.

21. The circuit as claimed in claim 13, wherein the first voltage source is VSS, and the first electrostatic discharge clamp circuit is coupled to a bulk and the first voltage source at one end and to a gate at another end of a second transistor to protect the second transistor from at least a charged device model electrostatic discharge.

22. The circuit as claimed in claim 21, further comprising,

a second electrostatic discharge clamp circuit having at least one bi-directional silicon diode including a third silicon diode and a fourth silicon diode,

wherein an n-type portion of the third silicon diode is coupled to a p-type portion of the fourth silicon diode and a p-type portion of the third silicon diode is coupled to an n-type portion of the fourth silicon diode, and

wherein the second electrostatic discharge clamp circuit is coupled to VDD and a bulk at one end and to a gate at another end of a first transistor.

23. The circuit as claimed in claim 22, in which a drain of the first transistor is coupled to a drain of the second transistor.

24. The circuit as claimed in claim 13, further comprising a second voltage source coupled to the first electrostatic discharge clamp circuit at a different end than the first voltage source, wherein the first voltage source is VDD and the second voltage source is VSS for providing electrostatic discharge protection.

25. The circuit as claimed in claim 13, further comprising a third voltage source coupled to the first electrostatic discharge clamp circuit, wherein the first voltage source provides a different voltage than that of the third voltage source.

26. The circuit as claimed in claim 25, wherein the third voltage source provides an input/output VDD voltage and the first voltage source provides a VDD voltage internal to the circuit.

27. The circuit as claimed in claim 25, wherein the third voltage source provides an input/output VSS voltage and the first voltage source provides a VSS voltage internal to the circuit.

13. An integrated circuit, comprising:

a signal pad;

a first voltage source; and

a first electrostatic discharge clamp circuit, coupled to the first voltage source, having at least one bi-directional silicon diode including a first silicon diode and a second silicon diode, wherein an n-type portion of the first silicon diode is coupled to a p-type portion of the second silicon diode and a p-type portion of the first silicon diode is coupled to an n-type portion of the second silicon diode, and

wherein the at least one bi-directional silicon diode is responsive to one of a positive electrostatic discharge or a negative electrostatic discharge.