Multistandard video decoder and decompression system for processing encoded bit streams including pipeline processing and methods relating thereto

• US 20020066007A1
• Filed: 02/05/2001
• Published: 05/30/2002
• Est. Priority Date: 06/30/1992
• Status: Active Grant

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Wise, Adrian P., Jones, Anthony M., Boyd, Kevin J., Finch, Helen R., Robbins, William P., Sotheran, Martin W., Claydon, Anthony Peter J.
• Granted Patent: US 6,950,930 B2
• Time in Patent Office: Days
• US Class Current: 712/300
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A pipeline video decoder and decompression system handles a plurality of separately encoded bit streams arranged as a single serial bit stream of digital bits and having separately encoded pairs of control codes and corresponding data carried in the serial bit stream. The pipeline system employs a plurality of interconnected stages to decode and decompress the single bit stream, including a start code detector. When in a search mode, the start code detector searches for a specific start code corresponding to one of multiple compression standards. The start code detector responding to the single serial bit stream generates control tokens and data tokens. A respective one of the tokens includes a plurality of data words. Each data word has an extension bit which indicates a presence of additional words therein. The data words are thereby unlimited in number. A token decode circuit positioned in certain of the stages recognizes certain of the tokens as control tokens pertinent to that stage and passes unrecognized control tokens to a succeeding stage. A reconfigurable decode and parser processing means positioned in certain of the stages is responsive to a recognized control token and reconfigures a particular stage to handle an identified data token. Methods relating to the decoder and decompression system include processing steps relating thereto

Claims

1. A pipeline system for decoding a data stream of data having portions encoded according to different standards comprising:

a sequence of pipeline stages, at least one of the pipeline stages being reconfigurable to operate according to the different standards;

the at least one of the pipeline stages including processing circuitry with an active state which is entered when the data received by the at least one of the pipeline stages has a predetermined activation pattern, the predetermined activation pattern corresponding to one of the different standards;

the at least one of the pipeline stages including a state machine having a current state and a previous state; and

wherein the at least one of the pipeline stages is activated upon recognition of the predetermined activation pattern only upon a predetermined transition from the previous state to the current state.

2. The pipeline system of claim 1, wherein the processing circuitry has an inactive state, in which the at least one of the pipeline stages passes data to a following pipeline stage without processing.

3. The pipeline system of claim 1, wherein the sequence of pipeline stages includes at least one spatial decoder stage.

4. The pipeline system of claim 1, wherein the sequence of pipeline stages includes at least one temporal decoder stage.

5. The pipeline system of claim 1, wherein the at least one of the pipeline stages is a spatial decoder stage.

6. The pipeline system of claim 1, wherein the at least one of the pipeline stages is a temporal decoder stage.