LOW TEMPERATURE SILICON WAFER BOND PROCESS WITH BULK MATERIAL BOND STRENGTH

• US 20020076902A1
• Filed: 11/10/1998
• Published: 06/20/2002
• Est. Priority Date: 11/10/1998
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: GEUSIC, JOSEPH E.
• Granted Patent: US 6,423,613 B1
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/76251 using bonding techniques

Abstract

The present invention includes a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing a first article that has a semiconductor surface and a second article that has a semiconductor surface. The semiconductor surfaces are annealed with an energy source wherein energy is confined to the semiconductor surfaces. The annealed surfaces are bonded to each other.

Claims

1. A method for bonding one semiconductor surface to a second semiconductor surface, comprising:

providing an article that has a semiconductor surface;

providing a second article that has a semiconductor surface;

annealing the semiconductor surfaces with an energy source wherein energy from the energy source is substantially confined to the semiconductor surfaces; and

contacting the semiconductor surface of the article to the second semiconductor surface of the second article to form a bond.

2. The method of claim 1 and further including fabricating an integrated circuit on or within another surface of the article wherein the surface opposes the surface which is annealed.

3. The method of claim 2 wherein fabricating the integrated circuit is performed prior to annealing the semiconductor surfaces.

4. The method of claim 3 wherein the semiconductor surfaces are annealed at a temperature of at least about 600°

Centigrade while the integrated circuit temperature is within 15 to 25°

Centigrade of room temperature.

5. The method of claim 1 wherein the semiconductor surfaces are annealed with a laser pulse.

6. The method of claim 5 wherein the laser pulse is an incident optical pulse energy of approximately 243 joules.

7. The method of claim 5 wherein the laser pulse is generated by a q-switched ruby laser.

8. The method of claim 1 wherein annealing comprises exposing the energy source to the semiconductor surface incrementally over the semiconductor surface.

9. The method of claim 1 wherein annealing comprises exposing the energy source to the entire semiconductor surface in a single exposure.

10. The method of claim 1 and further including stripping any native oxide from at least one of the semiconductor surfaces prior to annealing.

11. The method of claim 1 wherein the articles are subjected to a vacuum prior to annealing.

12. The method of claim 11 wherein the articles are stored in an ultra clean environment prior to being subjected to a vacuum.

13. The method of claim 1 and further including treating at least one of the semiconductor surfaces to render the surface hydrophobic prior to annealing.

14. The method of claim 13 and further including bonding the treated surfaces to each other prior to annealing the surfaces.

15. The method of claim 14 and further including transferring the bonded treated surfaces to an ultra-high vacuum chamber.

16. The method of claim 15 and further including creating a vacuum within the chamber.

17. The method of claim 16 and further including separating the surfaces prior to annealing.

18. The method of claim 17 wherein the vacuum is approximately 3×

10<sup>−

9</sup> Torr.

20. The semiconductor device of claim 19 wherein the semiconductor wafers have a diameter of about 4 inches.

21. The semiconductor device of claim 20 wherein the integrated circuit element is comprised of aluminum.

22. The semiconductor device of claim 21 wherein the semiconductor devices are comprised of silicon.

24. The semiconductor of claim 23 wherein each of the bonded wafers has a surface that is available for use over its entirety.

25. The semiconductor of claim 24 wherein the element comprises one or more of aluminum, copper, or polysilicon.

27. The method of claim 26 wherein the energy source is pulsed.

28. The method of claim 26 wherein the energy is sequentially applied so that a sum of the fractions comprises substantially an entire surface of the wafer.

29. The method of claim 26 wherein the energy is applied as a fraction of energy as is applied to an entire wafer surface.

30. The method of claim 26 wherein each fraction to which energy is applied is approximately one-tenth of the surface of the wafer.

31. The method of claim 26 and further including mounting the silicon wafers on a stage.

32. The method of claim 31 wherein the stage is moveable in an x-axis and a y-axis in relation to a fixed energy source.

33. The method of claim 31 wherein the stage is fixed and the energy source is moveable.

34. The method of claim 33 and further including focusing energy from the energy source to impinge in a raster x and y movement across the wafer surface.

36. The semiconductor article of claim 35 wherein the p-type wafer and the n-type wafer have substantially the same crystallographic structure.

37. The semiconductor article of claim 35 wherein the orientations of the p-type wafer and the n-type wafer are aligned within approximately one degree.

38. The semiconductor article of claim 35 and further including a P-N junction.

40. The semiconductor article of claim 39 and further including a high voltage device or CMOS etched within the epitaxial layer.

19. A semiconductor device comprising:

a first semiconductor wafer and a second semiconductor wafer, each having an annular edge, the second wafer annealed to the first semiconductor wafer forming a bond, wherein the bond is substantially free of hydrogen or defects; and

an integrated circuit element positioned on or within the annular edge of one of the semiconductor wafers.

23. A semiconductor device comprising:

a first silicon wafer and a second silicon wafer bonded to the first silicon wafer; and

a circuit element positioned on or within the second silicon wafer that includes features which change when subjected to a temperature at which the first silicon wafer is bonded to the second wafer, wherein the features are free of any bonding temperature changes.

26. A method for bonding one semiconductor wafer to another semiconductor wafer in order to maximize area and volume of a bonded wafer, comprising:

providing first and second semiconductor wafers;

annealing surfaces of the semiconductor wafers with an energy source wherein energy from the energy source is substantially confined to the semiconductor surfaces and energy is sequentially applied to a fraction of each of the surfaces; and

bonding the annealed surfaces to each other.

35. A semiconductor article comprising a p-type silicon wafer and an n-type silicon wafer wherein the p-type silicon wafer is bonded to the n-type silicon wafer.

39. A semiconductor article comprising an epitaxial layer, an insulator layer underlying the epitaxial layer, a silicon layer underlying the insulator layer wherein the silicon layer comprises one silicon wafer bonded to a second silicon wafer.