Universal serial bus (USB) interface for mass storage device

• US 20020081873A1
• Filed: 11/16/2001
• Published: 06/27/2002
• Est. Priority Date: 11/17/2000
• Status: Active Grant

• Current Assignee: USB Bridge Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Clark, Gordon R., Holland, Stephen D., Harris, David H.
• Granted Patent: US 7,231,485 B2
• Time in Patent Office: Days
• US Class Current: 439/79
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 3/0607 by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
• CPC Class Codes: G06F 3/0661 Format or protocol conversion arrangements
• CPC Class Codes: G06F 3/0676 Magnetic disk device

Abstract

A mass storage device motherboard or secondary board includes a bridging circuit. The bridging circuit converts signals from the mass storage device into USB signals. The bridging circuit can be provided by a chip that converts ATA/ATAPI signals into USB signals.

Claims

1. A method of communicating with a mass storage device, comprising:

receiving ATA/ATAPI signals from a mass storage device into a bridging circuit;

converting the ATA/ATAPI signals from the mass storage device into USB signals using the bridging circuit; and

outputting the USB signals from the bridging circuit.

2. A method according to claim 1, wherein the bridging circuit is provided in a single, bridging chip.

3. A method according to claim 1, wherein the bridging circuit is provided on a motherboard of the mass storage device.

4. A method according to claim 1, wherein the bridging circuit is provided on a secondary board.

5. A method according to claim 4, wherein a mass storage device motherboard outputs ATA/ATAPI signals, and wherein the secondary board receives the ATA/ATAPI signals from the mass storage device motherboard and converts them into USB signals.

6. A motherboard for a mass storage device, said motherboard comprising:

input logic configured to receive an input signal from a read unit of the mass storage device;

a bridging circuit configured to receive the input signal from the input logic and convert the input signal into a USB signal; and

output circuitry configured to output the USB signal from the motherboard.

7. A mass storage device motherboard according to claim 6, wherein the bridging circuit comprises a bridging chip for converting the input signal into the USB signal.

8. A mass storage device motherboard according to claim 6, wherein the bridging chip comprises:

an ATA/ATAPI interface configured to receive ATA/ATAPI signals from the input logic;

a disk interface configured to receive ATA/ATAPI signals from the ATA/ATAPI interface;

a serial interface engine; and

a USB physical interface transceiver configured to receive signals from the serial interface engine and output USB signals to a USB interface.

9. A secondary board configured to enable communication between a mass storage device motherboard and a host motherboard, said secondary board comprising:

a connector port for receiving signals from the mass storage device motherboard;

a bridging circuit for converting signals from the mass storage device motherboard into USB signals; and

a USB connector port for outputting the USB signals to the host motherboard.

10. A secondary board according to claim 9, wherein the bridging circuit comprises a bridging chip configured to translate the signals from the mass storage device motherboard into USB signals.

11. A secondary board according to claim 10, wherein the bridging chip comprises a USB physical interface transceiver, a serial interface engine, and a disk interface.

12. A secondary board according to claim 11, wherein the disk interface receives ATA/ATAPI signals through an ATA/ATAPI interface, and wherein the ATA/ATAPI signals are converted into USB 2.0 signals and are output to a USB Interface through the USB physical interface transceiver.

14. A chip according to claim 13, wherein said input comprises an ATA/ATAPI interface arranged to receive the ATA/ATAPI signals and a disk interface configured to receive ATA/ATAPI signals from the ATA/ATAPI interface;

wherein said conversion logic comprises a serial interface engine and a USB physical interface transceiver, said interface transceiver being configured to receive signals from the serial interface engine and output USB signals to a USB interface.

15. A chip according to claim 13, wherein the chip is located on a mass storage device motherboard.

16. A chip according to claim 13, wherein the chip is located on a secondary board.

17. A chip according to claim 16, wherein the secondary board is arranged to receive ATA/ATAPI signals from a motherboard of the mass storage device.

19. A method of converting signals according to claim 18, wherein said bridging chip is located on a motherboard of the mass storage device.

20. A method of converting signals according to claim 18, wherein the bridging chip is located on a secondary board arranged in communication with a motherboard of the mass storage device.

13. A bridging chip comprising:

an input configured to receive ATA/ATAPI signals;

conversion logic configured to convert the ATA/ATAPI signals into USB signals; and

an output configured to output the USB signals.

18. A method of converting signals from a mass storage device into USB signals, said method comprising:

receiving a signal from a mass storage device into a bridging chip;

converting the signal from the mass storage device into a USB signal;

outputting the USB signal from the bridging chip.