TECHNIQUE TO PRODUCE ISOLATED JUNCTIONS BY FORMING AN INSULATION LAYER

• US 20020086510A1
• Filed: 12/29/2000
• Published: 07/04/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Roberds, Brian
• Granted Patent: US 6,399,973 B1
• Time in Patent Office: Days
• US Class Current: 438/587
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A method for isolating a source and a drain in an MOS transistor by forming an insulation layer adjacent to the source and an insulation layer adjacent to the drain, and an apparatus produced from such a method.

Claims

1. A method comprising:

removing a portion of a semiconductor substrate adjacent to a gate stack in order to form a source region and a drain region;

forming an insulation layer on exposed portions of the semiconductor substrate within the source and drain regions; and

forming a source and a drain by depositing material in the source and drain regions.

2. The method of claim 1, wherein the removing includes a first removal, the first removal being a vertical anisotropic etch into the semiconductor substrate, self aligned with the gate stack, forming a first recess region and a second recess region, a region between the first and second recess regions defines a channel having a first sidewall and a second sidewall.

3. The method of claim 2, wherein a set of sidewall spacers are formed adjacent to the channel in the first and second recess regions to protect the first and second sidewalls of the channel.

4. The method of claim 3, wherein the removing further includes a second removal, the second removal being a vertical anisotropic etch into the semiconductor substrate aligned with the sidewall spacers forming the source and drain regions.

5. The method of claim 4, wherein the sidewall spacers are removed and a source tip is formed in the source region adjacent to the first sidewall of the channel and a drain tip is formed in the drain region adjacent to the second sidewall of the channel.

6. The method of claim 5, wherein the source and drain have a graded dopant distribution.

7. A method comprising:

removing a first portion of a semiconductor substrate adjacent to a gate stack in order to form a first recess region and a second recess region, a region between the first and second recess regions defines a channel having a first sidewall and a second sidewall;

forming a set of sidewall spacers adjacent to the channel in the first and second recess regions to protect the first and second sidewalls of the channel;

removing a second portion of the semiconductor substrate adjacent to the sidewall spacers in order to form a source region and a drain region;

forming an insulation layer on exposed portions of the semiconductor substrate within the source and drain regions; and

forming a source and a drain by depositing material in the source and drain regions.

8. The method of claim 7, wherein the sidewall spacers are removed and a source tip is formed in the source region adjacent to the first sidewall of the channel and a drain tip is formed in the drain region adjacent to the second sidewall of the channel.

9. The method of claim 8, wherein the source and drain have a graded dopant distribution.

10. A method comprising:

forming a semiconductor substrate above an insulator;

removing a portion of the semiconductor substrate adjacent to a gate stack in order 4 to form a source region and a drain region;

forming an insulation layer on exposed portions of the semiconductor substrate within the source and drain regions; and

forming a source and a drain by depositing material in the source and drain regions.

11. The method of claim 10, wherein the removing includes a first removal, the first removal being a vertical anisotropic etch into the semiconductor substrate, self-aligned with the gate stack, forming a first recess region and a second recess region, a region between the first and second recess regions defines a channel having a first sidewall and a second sidewall.

12. The method of claim 11, wherein a set of sidewall spacers are formed adjacent to the channel in the first and second recess regions to protect the first and second sidewalls of the channel.

13. The method of claim 12, wherein the removing further includes a second removal, the second removal being a vertical anisotropic etch into the semiconductor substrate aligned with the sidewall spacers forming the source and drain regions.

14. The method of claim 13, wherein the sidewall spacers are removed and a source tip is formed in the source region adjacent to the first sidewall of the channel and a drain tip is formed in the drain region adjacent to the second sidewall of the channel.

15. The method of claim 14, wherein the source and drain have a graded dopant distribution.

17. The method of claim 16, wherein the source and drain have a graded dopant distribution.

18. The method of claim 17, wherein the first portion of the semiconductor substrate is removed by a timed vertical anisotropic etch into the semiconductor substrate, self aligned with the gate stack, forming the first and second recess regions.

19. The method of claim 18, wherein the second portion of the semiconductor substrate is removed by a timed vertical anisotropic etch into the semiconductor substrate aligned with the sidewall spacers forming the source and drain regions.

16. A method comprising:

removing a first portion of a semiconductor substrate adjacent to a gate stack in order to form a first recess region and a second recess region, a region between the first and second recess regions defines a channel having a first sidewall and a second sidewall;

forming a source tip in the first recess region adjacent to the first sidewall of the channel and a drain tip in the second recess region adjacent to the second sidewall of the channel;

forming a set of sidewall spacers adjacent to the source tip and the drain tip in the first and second recess regions;

removing a second portion of the semiconductor substrate adjacent to the sidewall spacers in order to form a source region and a drain region;

forming an insulation layer on exposed portions of the semiconductor substrate within the source and drain regions; and

forming a source and a drain by depositing material in the source and drain regions.

20. An apparatus comprising:

a semiconductor substrate;

a source region and a drain region formed by removing a portion of the semiconductor substrate adjacent to the gate stack;

an insulation layer formed on exposed portions of the semiconductor substrate within the source and drain regions; and

a source and a drain formed by depositing material in the source and drain regions.

21. The apparatus of claim 20, further comprising a first recess region and a second recess region formed by a vertical anisotropic etch, self aligned with the gate stack, into in the semiconductor substrate, the area between the first and second recess regions defining a channel having a first sidewall and a second sidewall.

22. The apparatus of claim 21, further comprising a set of sidewall spacers formed adjacent to the channel to protect the first and second sidewalls of the channel.

23. The apparatus of claim 22, wherein the source and drain regions are formed by a vertical anisotropic etch into the semiconductor substrate aligned with the sidewall spacers.

24. The apparatus of claim 23, further comprising a source tip formed, after a removal of the sidewall spacers, adjacent to the first sidewall of the channel and a drain tip formed, after the removal of the sidewall spacers, adjacent to the second sidewall of the channel.

25. The apparatus of claim 24, wherein the source and drain have a graded dopant distribution.