CPU power sequence for large multiprocessor systems

• US 20020087906A1
• Filed: 12/29/2000
• Published: 07/04/2002
• Est. Priority Date: 12/29/2000
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Mar, Clarence Y., Jenne, John E., Olarig, Sompong P.
• Granted Patent: US 6,792,553 B2
• Time in Patent Office: Days
• US Class Current: 713/330
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/305 in the event of power-supply fluctuations

Abstract

A computer system includes a power supply coupled to a control logic, the power supply including a power_good output signal and Power output lines. The power_good signal notifies the control logic when the Power output lines have stabilized. The computer system also includes a plurality of voltage regulator modules (“VRM”) coupled to the control logic, wherein each VRM receives a power good signal from the control logic. A plurality of processors is also present in the computer system, each of the processors coupled to a VRM. Each of the VRMs transmits voltage to a processor to power-on the processor. Each VRM also transmits to its processor and to the control logic a voltage regulator module power good (“VRMP_G”) signal. The control logic includes means to control the sequential power-on of the processors so as to reduce the current sourcing requirements of the power supply and eliminate power supply surges.

Claims

1. A computer system, comprising:

a power supply coupled to a control logic, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control logic when the Power output lines have stabilized;

a plurality of voltage regulator modules (“

VRM”

) coupled to said control logic, wherein each VRM receives a second control signal from the control logic indicating that the Power lines have stabilized; and

a plurality of processors, each of said processors coupled to a VRM, wherein each of said VRMs transmits voltage to a processor to power-on the processor.

2. The computer system of claim 1 wherein each of said VRMs transmits to its processor and to the control logic a third control signal, said third control signal indicating that the VRM voltage output lines have stabilized.

3. The computer system of claim 1 wherein said power supply asserts the first control signal after the power supply output lines have stabilized and said control logic places all processors of the computer system into a reset state and drives a second control signal to a first VRM.

4. The computer system of claim 3 wherein said control logic waits a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels and said VRM drives a third control signal to the VRM'"'"'s processor and the control logic after the VRM voltage output lines have stabilized.

5. The computer system of claim 4 wherein said control logic waits a second programmable delay for the processor to reach a stable electrical state, determines whether all processors are powered on, and if all processors are not powered on drives another second control signal to the next VRM and repeats the steps of claim 4 or if all processors are powered on takes all processors out of reset and begins hardware initialization after waiting a third programmable delay.

6. The computer system of claim 1 wherein said power supply asserts the first control signal after the power supply output lines have stabilized and said control logic places all processors of the computer system into a reset state and drives a second control signal to a first VRM.

7. The computer system of claim 6 wherein said control logic waits a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels and for the processor to power-on and reach a stable electrical state.

8. The computer system of claim 7 wherein said control logic determines whether all processors are powered on, and if all processors are not powered on drives another second control signal to the next VRM and repeats the steps of claim 7 or if all processors are powered on takes all processors out of reset and begins hardware initialization after waiting a second programmable delay.

9. A method of powering on processors in a computer system that reduces the current source requirements of the computer system'"'"'s power supply, comprising the steps of:

a) asserting a first control signal from the power supply after output lines of the power supply have stabilized;

b) placing all processors of the computer system into a reset state; and

c) driving a second control signal to a first voltage regulator module (“

VRM”

).

10. The method of claim 9 further comprising the steps of:

d) waiting a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels; and

e) driving a third control signal to the processor coupled to the VRM and to the control logic after the VRM voltage output lines have stabilized.

11. The method of claim 10 further comprising the steps of:

f) waiting a second programmable delay for the processor coupled to the VRM to reach a stable electrical state;

g) determining whether all processors in the computer system are powered on;

h) driving another second control signal to the next VRM and repeating steps d) through g) if all processors in the computer system are not powered on; and

i) taking all processors out of reset and beginning hardware initialization if all processors are powered on after waiting a third programmable delay.

13. The computer system of claim 12 wherein each of said VRMs transmits to its processor and to the intelligent power supply a second control signal, said second control signal indicating that the VRM voltage output lines have stabilized.

14. The computer system of claim 12 wherein said intelligent power supply places all processors of the computer system into a reset state and drives a first control signal to a first VRM.

15. The computer system of claim 14 wherein said intelligent power supply waits a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels and said VRM drives a third control signal to the VRM'"'"'s processor and the control logic after the VRM voltage output lines have stabilized.

16. The computer system of claim 15 wherein said control logic waits a second programmable delay for the processor to reach a stable electrical state, determines whether all processors are powered on, and if all processors are not powered on drives another first control signal to the next VRM and repeats the steps of claim 15 or if all processors are powered on takes all processors out of reset and begins hardware initialization after waiting a third programmable delay.

17. The computer system of claim 12 wherein said intelligent power supply places all processors of the computer system into a reset state and drives a first control signal to a first VRM.

18. The computer system of claim 17 wherein said intelligent power supply waits a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels and for the processor to power-on and reach a stable electrical state.

19. The computer system of claim 18 wherein said intelligent power supply determines whether all processors are powered on, and if all processors are not powered on drives another first control signal to the next VRM and repeats the steps of claim 18 or if all processors are powered on takes all processors out of reset and begins hardware initialization after waiting a second programmable delay.

12. A computer system, comprising:

an intelligent power supply including a control logic, said power supply including a plurality of first control signals and Power output lines;

a plurality of voltage regulator modules (“

VRM”

) coupled to said intelligent power supply, wherein each VRM receives a first control signal from the intelligent power supply; and

a plurality of processors, each of said processors coupled to a VRM, wherein each of said VRMs transmits voltage to a processor to power-on the processor.

20. A computer system, comprising:

a power supply coupled to a control module, said power supply including a first control signal and Power output lines, wherein said first control signal notifies the control module when the Power output lines have stabilized;

a plurality of voltage regulator modules (“

VRM”

) coupled to said control module, wherein each VRM receives a second control signal from the control module indicating that the Power lines have stabilized; and

a plurality of computer servers organized in racks in a cabinet, each of said computer servers coupled to a VRM, wherein each of said VRMs transmits voltage to a computer server to power-on the computer server.

21. The computer system of claim 20 wherein each of said VRMs transmits to its computer server and to the control module a third control signal, said third control signal indicating that the VRM voltage output lines have stabilized.

22. The computer system of claim 20 wherein said power supply asserts the first control signal after the power supply output lines have stabilized and said control module places all computer servers of the computer system into a reset state and drives a second control signal to a first VRM.

23. The computer system of claim 22 wherein said control module waits a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels and said VRM drives a third control signal to the VRM'"'"'s computer server and the control module after the VRM voltage output lines have stabilized.

24. The computer system of claim 23 wherein said control module waits a second programmable delay for the computer server to reach a stable electrical state, determines whether all computer servers are powered on, and if all computer servers are not powered on drives another second control signal to the next VRM and repeats the steps of claim 23 or if all computer servers are powered on takes all computer servers out of reset and begins hardware initialization after waiting a third programmable delay.

25. The computer system of claim 20 wherein said power supply asserts the first control signal after the power supply output lines have stabilized and said control module places all computer servers of the computer system into a reset state and drives a second control signal to a first VRM.

26. The computer system of claim 25 wherein said control module waits a first programmable delay for the VRM to stabilize its voltage output lines to appropriate levels and for the computer server to power-on and reach a stable electrical state.

27. The computer system of claim 26 wherein said control module determines whether all computer servers are powered on, and if all computer servers are not powered on drives another second control signal to the next VRM and repeats the steps of claim 26 or if all computer servers are powered on takes all computer servers out of reset and begins hardware initialization after waiting a second programmable delay.

28. The computer system of claim 27 wherein if all the computer servers in a cabinet are powered on, the control module asserts a completion signal to another control module in another cabinet including another power supply in which computer servers that are not powered on, and repeats the steps of claim 22 through claim 27 until all cabinets of the computer system are powered on.