Display device

• US 20020089496A1
• Filed: 01/04/2002
• Published: 07/11/2002
• Est. Priority Date: 01/10/2001
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Numao, Takaji
• Granted Patent: US 6,853,370 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2300/0828 forming a digital to analog [D/A] conversion circuit
• CPC Class Codes: G09G 2300/0857 Static memory circuit, e.g. flip-flop
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/22 using controlled light sources
• CPC Class Codes: G09G 3/3258 with pixel circuitry controlling the voltage across the light-emitting element
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence

Abstract

In a display device, an active element (A) captures data of a signal line into a memory element while the active element (A) is selected by a selection line, and the active element that makes up an electro-optical element applies a voltage of a reference line to an organic EL element according to storage contents of the memory element, thereby performing storage holding operation for each pixel while preventing rewriting of the same data so as to save power. In order to realize multi-gray-level display, the display device reduces the number of wires and power consumption. In order to do so, more specifically, two or more memory elements are provided in accordance with a desired gray-scale for display. Further provided are active elements (B), each of which is associated with each memory element, and bit selection lines routed to be shared by control input terminals of the active elements (B) having the equivalent bit order to each other, either one of the bit selection lines being selected at a time. Data is written during a non-selection period, and the bit selection line is selected only for the duration of weighted bit during a selection period.

Claims

1. A display device, comprising:

electro-optical elements, each of which is disposed in each area arranged in a matrix;

active elements (A), each of which is provided in said each area; and

memory elements, each of which captures data from a signal line via said active element (A) in between, and activates each said electro-optical element for display by output,

wherein;

two or more said memory elements associated with said each electro-optical element are provided with respect to each of said signal lines, and

said each electro-optical element is activated for display by output, in part or in full, from said two or more memory elements which are provided in association with said electro-optical element.

18. The display device set forth in claim 1, wherein said memory element is made up of a ferroelectric thin-film capacitor.

2. A display device, comprising:

active elements (A) connected to selection lines and signal lines;

memory elements, each of which captures data from the signal line via said active element (A) in between;

electro-optical elements, each of which performs display in accordance with storage contents of said memory element; and

active elements (B), each of which is provided in association with each of said memory elements,

wherein the number of said memory elements, which are provided in association with the respective electro-optical elements and with respect to each of said signal lines, is the same as the number of bits which are associated with at least a portion of desired gray-levels and/or images for display, and

the display device further comprising bit selection lines which are routed so as to be shared by control input terminals of said active elements (B) having the equivalent bit order to each other, either one of the bit selection lines being selected at a time for each bit order, the bit selection lines activating said active elements (B) to store the data in the associated memory element via said active element (A) during a selection period of the selection line, and to output the data stored in the associated memory element with respect to said electro-optical element during a non-selection period of the selection line.

6. The display device set forth in claim 2, wherein each of said electro-optical elements is aligned in a matrix, and said bit selection line is shared by adjacent row intervals.

10. The display device set forth in claim 6, wherein said bit selection line is divided into two groups, and the divided bit selection lines are disposed at row intervals in a dispersed manner.

14. The display device set forth in claim 2, further comprising decode means for decoding selection data of said bit selection line.

19. The display device set forth in claim 2, wherein said memory element is made up of a ferroelectric thin-film capacitor.

3. A display device, comprising:

active elements (A) connected to selection lines and signal lines;

memory elements, each of which captures data from the signal line via said active element (A) in between while said active element (A) is selected by the selection line;

electro-optical elements, each of which performs display in accordance with storage contents of said memory element; and

active elements (C), each of which is provided in association with said each memory element between said memory element and said electro-optical element,

wherein the number of said memory elements, which are provided in association with said respective electro-optical elements and with respect to each of said signal lines, is the same as the number of bits which are associated with at least a portion of desired gray-levels and/or images for display, and said memory elements are respectively provided in association with the different selection lines via the different active elements (A) in between,

the display device further comprising bit selection lines which are routed so as to be shared by control input terminals of said active elements (C) having the equivalent bit order to each other, either one of the bit selection lines being selected at a time for each bit order, the bit selection lines activating said active elements (C) to output the data stored in the associated memory element with respect to said electro-optical element.

7. The display device set forth in claim 3, wherein each of said electro-optical elements is aligned in a matrix, and said bit selection line is shared by adjacent row intervals.

11. The display device set forth in claim 7, wherein said bit selection line is divided into two, and the divided bit selection lines are disposed at row intervals in a dispersed manner.

15. The display device set forth in claim 3, further comprising decode means for decoding selection data of said bit selection line.

20. The display device set forth in claim 3, wherein said memory element is made up of a ferroelectric thin-film capacitor.

4. A display device, comprising:

active elements (A) connected to selection lines and signal lines;

memory elements, each of which captures data from the signal line via said active element (A) in between while said active element (A) is selected by the selection line; and

electro-optical elements, each of which performs display in accordance with storage contents of said memory element,

wherein;

the number of said memory elements, which are provided in association with said respective electro-optical elements and with respect to each of said signal lines, is the same as the number of bits which are associated with at least a portion of desired gray-levels for display, and said memory elements are respectively provided in association with the different selection lines via the different active elements (A) in between, and

said respective electro-optical elements are activated for display by total output of a plurality of said memory elements which are formed in association with said electro-optical elements.

8. The display device set forth in claim 4, wherein each of said electro-optical elements is aligned in a matrix, and said bit selection line is shared by adjacent row intervals.

12. The display device set forth in claim 8, wherein said bit selection line is divided into two, and the divided bit selection lines are disposed at row intervals in a dispersed manner.

16. The display device set forth in claim 4, further comprising decode means for decoding selection data of said bit selection line.

21. The display device set forth in claim 4, wherein said memory element is made up of a ferroelectric thin-film capacitor.

5. A display device, comprising:

active elements (A) connected to selection lines and signal lines;

memory elements, each of which captures data from the signal line via said active element (A) in between;

electro-optical elements, each of which performs display in accordance with storage contents of said memory element; and

active elements (B), each of which is provided in association with said each memory element,

wherein the number of said memory elements, which are provided in association with said respective electro-optical elements and with respect to each of said signal lines, is the same as the number of bits which are associated with at least a portion of desired gray-levels for display,

the display device further comprising bit selection lines which are routed so as to be shared by control input terminals of said active elements (B) having the equivalent bit order to each other, either one of the bit selection lines being selected at a time for each bit order, the bit selection lines activating said active elements (B) to store the data in the associated memory element via said active element (A) during a selection period of the selection line,

said respective electro-optical elements being activated for display by total output of a plurality of said memory elements which are formed in association with said electro-optical elements.

9. The display device set forth in claim 5, wherein each of said electro-optical elements is aligned in a matrix, and said bit selection line is shared by adjacent row intervals.

13. The display device set forth in claim 9, wherein said bit selection line is divided into two, and the divided bit selection lines are disposed at row intervals in a dispersed manner.

17. The display device set forth in claim 5, further comprising decode means for decoding selection data of said bit selection line.

22. The display device set forth in claim 5, wherein said memory element is made up of a ferroelectric thin-film capacitor.