Radiation hardened silicon-on-insulator (SOI) transistor having a body contact

• US 20020096719A1
• Filed: 03/05/2002
• Published: 07/25/2002
• Est. Priority Date: 08/03/1999
• Status: Active Grant

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Inventors: Dockerty, Robert, Hurt, Michael J., Brady, Frederick T., Haddad, Nadim
• Granted Patent: US 6,716,728 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: G06Q 40/02 Banking, e.g. interest calculation or account maintenance credit or loans G06Q40/03
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A radiation hardened silicon-on-insulator transistor is disclosed. A dielectric layer is disposed on a substrate, and a transistor structure is disposed on the dielectric layer. The transistor structure includes a body region, a source region, a drain region, and a gate layer. The body region is formed on a first surface portion of the dielectric layer, the source region is formed on a second surface portion of the dielectric layer contiguous with the first surface portion, the drain region is formed on a third surface portion of the dielectric layer contiguous with the first surface portion, and the gate layer overlies the body region and being operative to induce a channel in that portion of the body region disposed between and adjoining the source region and the drain region. In addition, multiple diffusions are placed across two edges of the source region. These diffusions are ohmically connected to the body region via a body contact, and these diffusions are also connected to the source region by a self-aligned salicide.

Claims

1. A field effect transistor comprising:

a dielectric layer disposed on a substrate; and

a transistor structure disposed on said dielectric layer, wherein said transistor structure includes;

a body region formed on a first surface portion of said dielectric layer;

a source region formed on a second surface portion of said dielectric layer contiguous with said first surface portion;

a drain region formed on a third surface portion of said dielectric layer contiguous with said first surface portion;

a gate layer overlying said body region and being operative to induce a channel in that portion of said body region disposed between and adjoining said source region and said drain region; and

a plurality of diffusions placed across two edges of said source region, wherein said diffusions are ohmically connected to said body region via a body contact.

2. The field effect transistor according to claim 1, wherein said diffusions are electrically connected to said source region by a salicide.

3. The field effect transistor according to claim 1, wherein said body region and said plurality of diffusions are P-type doped, wherein said source region and drain region are N-type doped.

4. The field effect transistor according to claim 1, wherein said body region and said plurality of diffusions are N-type doped, wherein said source region and drain region are P-type doped.

5. The field effect transistor according to claim 1, wherein a plurality areas of said gate layer are extended to connect to said plurality of diffusions for minimum length devices.

6. The field effect transistor according to claim 1, wherein said field effect transistor is a silicon-on-insulator transistor.

7. A method for providing a body contact for a field effect transistor, wherein said field effect transistor is disposed on a dielectric layer situated on top of a substrate, wherein said field effect transistor includes a body region formed on a first surface portion of said dielectric layer, a source region formed on a second surface portion of said dielectric layer contiguous with said first surface portion, a drain region formed on a third surface portion of said dielectric layer contiguous with said first surface portion, a gate layer overlying said body region and being operative to induce a channel in that portion of said body region disposed between and adjoining said source region and said drain region, said method comprising:

placing a plurality of diffusions across two edges of said source region of said field effect transistor; and

ohmically connecting said diffusions to said body region of said field effect transistor via a body contact.

8. The method according to claim 7, wherein said method further includes electrically connecting said plurality of diffusions to said source region by a salicide.

9. The method according to claim 7, wherein said body region and said plurality of diffusions are P-type doped, wherein said source region and drain region are N-type doped.

10. The method according to claim 7, wherein said body region and said plurality of diffusions are N-type doped, wherein said source region and drain region are P-type doped.

11. The method according to claim 7, wherein a plurality areas of said gate layer are extended to connect to said plurality of diffusions for minimum length devices.

12. The method according to claim 7, wherein said field effect transistor is a silicon-on-insulator transistor.