ELECTROLESS NI/PD/AU METALLIZATION STRUCTURE FOR COPPER INTERCONNECT SUBSTRATE AND METHOD THEREFOR

• US 20020096765A1
• Filed: 01/22/2001
• Published: 07/25/2002
• Est. Priority Date: 01/22/2001
• Status: Active Grant

• Current Assignee: Flipchip International LLC (Tianshui Huatian Technology Company Limited)
• Original Assignee: Flip Chip Technologies, LLC
• Inventors: Stepniak, Dave Charles, Ling, Jamin
• Granted Patent: US 6,445,069 B1
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A nickel/palladium/gold metallization stack is formed upon connection pads of integrated circuits at the wafer level through an electroless plating method. The metallization stack can be formed over copper or aluminum interconnect pads; the lower nickel layer bonds securely to the copper or aluminum interconnect pads, while the intermediate palladium layer serves as a diffusion barrier for preventing the nickel from out-diffusing during subsequent thermal cycles. The upper gold layer adheres to the palladium and readily receives a variety of interconnect elements, including gold bumps, gold wire bonds, solder bumps, and nickel bumps. The electroless plating process permits connection pads to be formed using fine geometries, and allows adjacent connection pads to be formed within 5 micrometers of each other.

Claims

1. An integrated circuit structure comprising in combination:

a. a semiconductor wafer having an upper surface, the semiconductor wafer having a plurality of identical die formed therein, each of the identical die having a plurality of semiconductor devices formed therein upon the surface of the semiconductor wafer;

b. a patterned layer of interconnect metal formed upon the upper surface of the semiconductor wafer for electrically interconnecting the plurality of semiconductor devices formed within each such die, said patterned layer of interconnect metal including connection pads for making electrical connection to circuitry external to the semiconductor wafer;

c. a patterned layer of nickel plated over each connection pad for mechanically and electrically bonding to the interconnect metal forming such connection pad;

d. a patterned layer of palladium plated over the patterned layer of nickel above each connection pad for preventing the nickel from diffusing outwardly through the palladium during subsequent heating cycles; and

e. a patterned layer of gold plated over the patterned layer of palladium above each connection pad to facilitate the joinder of such connection pad with a connection element.

2. The integrated circuit structure recited by claim 1 wherein said connection element is a gold bump.

3. The integrated circuit structure recited by claim 1 wherein said connection element is a gold wire bond.

4. The integrated circuit structure recited by claim 1 wherein said connection element is a solder bump.

5. The integrated circuit structure recited by claim 1 wherein said connection element is a nickel bump.

6. The integrated circuit structure recited by claim 1 wherein the patterned layer of nickel is plated directly on top of the patterned layer of interconnect metal at each connection pad.

7. The integrated circuit structure recited by claim 1 wherein, upon each of said die, two of said connection pads are disposed within 5 micrometers of each other.

8. The integrated circuit structure recited by claim 1 wherein said patterned layer of nickel has a thickness that lies in the range of 0.5 micrometers and 20 micrometers.

9. The integrated circuit structure recited by claim 1 wherein said patterned layer of palladium has a thickness that lies in the range of 0.1 micrometers and 5 micrometers.

10. The integrated circuit structure recited by claim 1 wherein said patterned layer of gold has a thickness that lies in the range of 0.03 micrometers and 2 micrometers.

11. The integrated circuit structure recited by claim 1 wherein said patterned layer of interconnect metal is formed of copper.

12. The integrated circuit structure recited by claim 1 wherein said patterned layer of interconnect metal is formed of aluminum.

14. The process recited by claim 14 including the further step of joining a gold bump to the patterned layer of gold above at least one of said connection pads.

15. The process recited by claim 14 including the further step of joining a gold wire bond to the patterned layer of gold above at least one of said connection pads.

16. The process recited by claim 14 including the further step of joining a solder bump to the patterned layer of gold above at least one of said connection pads.

17. The process recited by claim 14 including the further step of joining a nickel bump to the patterned layer of gold above at least one of said connection pads.

18. The process recited by claim 14 wherein the patterned layer of nickel is plated directly on top of the patterned layer of copper metal at each connection pad.

19. The process recited by claim 14 wherein, upon each of said integrated circuit die, at least two of the connection pads are formed within 5 micrometers of each other.

20. The process recited by claim 14 wherein said step of forming a patterned layer of nickel produces a nickel layer having a thickness that lies in the range of 0.5 micrometers and 20 micrometers.

21. The process recited by claim 14 wherein said step of forming a patterned layer of palladium produces a palladium layer having a thickness that lies in the range of 0.1 micrometers and 5 micrometers.

22. The process recited by claim 14 wherein said step of forming a patterned layer of gold produces a gold layer having a thickness that lies in the range of 0.03 micrometers and 2 micrometers.

23. The process recited by claim 14 wherein said step of forming a patterned layer of interconnect metal upon the upper surface of the semiconductor wafer for electrically interconnecting the plurality of semiconductor devices includes the step of forming such patterned layer of interconnect metal from the metal copper.

24. The process recited by claim 14 wherein said process includes the further step of heating the semiconductor wafer following the step of forming the patterned layer of gold in order to thermal cycle the plurality of semiconductor devices formed within each such integrated circuit die.

13. A process for forming connection pads on a plurality of integrated circuit die formed in a semiconductor wafer, the semiconductor wafer having an upper surface, each of the integrated circuit die having a plurality of semiconductor devices formed therein upon the surface of the semiconductor wafer, said process including the steps of:

a. forming a patterned layer of interconnect metal upon the upper surface of the semiconductor wafer for electrically interconnecting the plurality of semiconductor devices formed within each such integrated circuit die, said patterned layer of interconnect metal including connection pads for making electrical connection to circuitry external to the semiconductor wafer;

b. following step a., forming a patterned layer of nickel by electroless plating over each connection pad for mechanically and electrically bonding to the interconnect metal at each such connection pad;

c. following step b., forming a patterned layer of palladium by electroless plating over the patterned layer of nickel above each connection pad for preventing the nickel from diffusing outwardly through the palladium during subsequent heating cycles; and

d. following step c., forming a patterned layer of gold by electroless plating over the patterned layer of palladium above each connection pad to facilitate the joinder of such connection pad with a connection element.