REFRESH CONTROL CIRCUIT FOR LOW-POWER SRAM APPLICATIONS

• US 20020097624A1
• Filed: 01/22/2001
• Published: 07/25/2002
• Est. Priority Date: 01/22/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kosonocky, Stephen, Hsu, Louis L., Wang, Li-Kong, Andersen, John E.
• Granted Patent: US 6,434,076 B1
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to the local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.

Claims

1. A semiconductor static random access memory (SRAM) system including one or more memory arrays, said system comprising;

a power management device associated with each memory array, each power management device comprising a first switching device for connecting a power source to a memory array during normal SRAM device operation and responsive to a low power mode signal for disconnecting said power source from said memory array during a low power mode of operation;

said power management device further comprising a second switching device for connecting a power source to a respective memory array; and

,

a refresh control device for independently controlling each said second switch device for selectively connecting and disconnecting said power source to a respective memory array during said low power mode of operation, whereby power consumption in said SRAM device is reduced during said low power mode.

2. The SRAM system as claimed in claim 1, wherein said first and second switch devices are MOS devices, said second switch device being smaller than said first switch device for slow switching during said low power mode.

3. The SRAM system as claimed in claim 2, wherein said power source includes a local power supply associated with each memory array and an external power supply, said first and second switch devices operative for connecting the external power supply to each said at least one local power supply.

4. The SRAM system as claimed in claim 1, wherein said refresh control device generates a periodic pulsed refresh control signal for periodically switching said external power source to a respective local power supply.

5. The SRAM system as claimed in claim 3, wherein said refresh control device simultaneously generates one or more pulse control signals for enabling simultaneous switching of each said second switch devices for connecting said power source to each said memory array during the low-power mode.

6. The SRAM system as claimed in claim 3, wherein said refresh control device sequentially generates one or more pulse control signals for connecting said power source to a respective local power supply of a memory array in a sequential manner during the low-power mode.

7. The SRAM system as claimed in claim 3, wherein said refresh control device includes a sensing mechanism for sensing a voltage of said local power supply during the low-power mode, wherein upon sensing of a local supply voltage level lower than a predetermined low-level voltage, said refresh control device activating said second switch to connect the external power supply to a respective local supply to thereby increase its voltage level.

8. The SRAM system as claimed in claim 7, wherein upon sensing of the local supply voltage level at a level higher than a predetermined high-level, said refresh control device deactivating said second switch to disconnect the external power supply from the local supply to thereby decrease its voltage level due to sub-array memory cell charge leakage.

9. The SRAM system as claimed in claim 8, further comprising a reservoir capacitor connected to a respective local power supply for replenishing any the leakage charge to the SRAM arrays.

10. The SRAM system as claimed in claim 4, wherein said generated pulsed refresh control signal has a pulse width ranging from 1 nsec to 100 nsec.

11. The SRAM system as claimed in claim 4, wherein said refresh control device comprises a timer circuit for generating said pulsed refresh control signal.

12. The SRAM system as claimed in claim 4, wherein said refresh control device further comprises a decoder device responsive to a control signals for indicating a specific memory array to be refreshed.

13. The SRAM system as claimed in claim 2, wherein said first switch device is a low resistance switch for operation during said active mode, and said second switch device is a high resistance switch to ensure a soft-refresh during said low power mode.

14. The SRAM system as claimed in claim 13, wherein said first switch device is a wide channel MOS transistor device having a channel width ranging anywhere from about 100 μ

m-5000 μ

m.

15. The SRAM system as claimed in claim 13, wherein said second switch device is a narrow channel MOS transistor device having a channel width ranging anywhere from about 1 μ

m-5 μ

m.

16. The SRAM system as claimed in claim 13, wherein said second switch device is a high-threshold voltage nMOS device having a threshold voltage ranging anywhere from about 0.6 V to 1V, wherein during said low-power mode, said second switch device functions to clamp said local supply level.

17. The SRAM system as claimed in claim 13, wherein said first switch device is a low-threshold voltage pMOS device having a threshold voltage ranging anywhere from about 0.3 to 0.6V.

18. The SRAM system as claimed in claim 4, wherein a refresh cycle time period for a memory array ranges from about 1 μ

sec to 5 μ

sec.

19. The SRAM system as claimed in claim 8, wherein said predetermined high-level of the local power supply voltage ranges anywhere between 0.6 V to 1 V and said predetermined low-level of the local power supply voltage ranges from 0.2 V to 0.4 V.

20. The SRAM system as claimed in claim 7, wherein said sensing mechanism includes:

a first comparing device for comparing said sensed local power supply level against said predetermined high-level voltage;

a second comparing device for comparing said sensed local power supply level against said predetermined low-level voltage, each of said comparing devices connected with said

means responsive to said first and second comparing devices for one of respectively deactivate and activate said second switch device for respectively disconnecting said external power supply from said local supply or connecting said external power supply to said local supply.

21. The SRAM system as claimed in claim 20, wherein said means responsive to said first and second comparing devices includes a flip-flop device.

22. The SRAM system as claimed in claim 1, further comprising ground wiring provided to shield noise among said one or more memory arrays.

25. The power management circuit for an SRAM device as claimed in claim 24, wherein said first switch mechanism and said voltage clamp device are responsive to a low power mode control signal for initiating said lower power mode.

26. The power management circuit for an SRAM device as claimed in claim 24, wherein said voltage clamp device includes a high-threshold voltage MOS transistor device having a threshold voltage ranging anywhere from about 0.6 V to 1V.

27. The power management circuit for an SRAM device as claimed in claim 24, wherein said first switch device is a low-threshold voltage MOS transistor device having a threshold voltage ranging anywhere from about 0.3 to 0.6V.

23. A power management circuit for an SRAM system including one or more memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to each local power supply during active mode of operation, said power management circuit comprising:

a switch mechanism for disconnecting the external power supply to each said at least one local power supply during a low power mode of operation; and

,

a refresh timing circuit implementing memory cell refresh operation by selectively connecting the external power supply to a respective local power supply during said low power mode, wherein, during said low power mode, said refresh circuit intentionally enables said local power supply to float and drift to a lower predetermined voltage level prior to said memory array refresh operation.

24. A power management circuit for an SRAM system including one or more memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to each local power supply during active mode of operation, said power management circuit comprising:

a first switch mechanism for disconnecting the external power supply to each said at least one local power supply during a low power mode of operation; and

,

a refresh timing circuit implementing a voltage clamp device for clamping said each respective local power supply at a predetermined voltage during said low power mode, said predetermined voltage being lower than said external supply voltage.