Thin-film semiconductor device and method of manufacturing the same

• US 20020102777A1
• Filed: 01/31/2002
• Published: 08/01/2002
• Est. Priority Date: 01/31/2001
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Sakaguchi, Kiyofumi, Yonehara, Takao
• Granted Patent: US 6,677,183 B2
• Time in Patent Office: Days
• US Class Current: 438/149
• CPC Class Codes: H01L 21/02203 the layer being porous
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02307 treatment by exposure to a liquid
• CPC Class Codes: H01L 21/02337 treatment by exposure to a gas or vapour
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 21/31675 of silicon
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01067 Holmium [Ho]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]

Abstract

This invention provides a method of manufacturing a thin-film semiconductor device by a smaller number of processes with reduced influence on a device formation layer at the time of separation. This manufacturing method includes the step of preparing a member having, on a separation layer, a semiconductor film having a semiconductor element and/or semiconductor integrated circuit, the step of forming kerfs from the semiconductor film side of the member, and the separation step of, after the kerf formation step, separating a desired region of the semiconductor element and/or semiconductor integrated circuit from the member.

Claims

1. A method of manufacturing a thin-film semiconductor device, comprising:

the step of preparing a member having, on a separation layer, a semiconductor film having a semiconductor element and/or semiconductor integrated circuit;

the step of forming kerfs from the semiconductor film side of the member; and

the separation step of, after the kerf formation step, separating a desired region of the semiconductor element and/or semiconductor integrated circuit from the member.

2. The method according to claim 1, wherein the separation step is performed by injecting a fluid into the kerfs.

3. The method according to claim 1, wherein the member is obtained by forming a porous layer on a surface of a semiconductor substrate, forming the semiconductor film on a surface of the porous layer, and then forming the semiconductor element and/or semiconductor integrated circuit.

4. The method according to claim 3, wherein the semiconductor film is formed on the surface of the porous layer after forming a protective film on inner walls of pores in the porous layer.

5. The method according to claim 1, wherein the member is obtained by forming the semiconductor element and/or semiconductor integrated circuit on a surface of a semiconductor substrate and implanting ions from the surface side to a predetermined depth to form the separation layer.

6. The method according to claim 3, wherein the semiconductor substrate is a single-crystal silicon substrate or a compound semiconductor substrate.

7. The method according to claim 5, wherein the semiconductor substrate is a single-crystal silicon substrate or a compound semiconductor substrate.

8. The method according to claim 1, wherein the kerfs are formed in the semiconductor film.

9. The method according to claim 1, wherein the kerfs are formed in a region formed in a process of forming the semiconductor element and/or semiconductor integrated circuit on the semiconductor film.

10. The method according to claim 1, wherein the kerfs are formed by one of dicing, etching, laser abrasion, ultrasonic cutter, and high-pressure jet.

11. The method according to claim 1, wherein the kerfs are formed such that bottom portions thereof are located in the separation layer or at an interface between the semiconductor film and the separation layer.

12. The method according to claim 1, wherein the member has the separation layer and semiconductor film on a semiconductor region, and the kerfs are formed such that bottom portions thereof are located at an interface between the separation layer and the semiconductor region or in the semiconductor region.

13. The method according to claim 2, wherein the separation step is performed by injecting a high-pressure fluid from the kerfs.

14. The method according to claim 2, wherein the separation step is performed by injecting the fluid comprising a liquid or a gas to at least some of the kerfs.

15. The method according to claim 14, wherein the separation step is performed by injecting the fluid from at least two of the kerfs around the desired region.

16. The method according to claim 1, wherein the separation step is performed under a static pressure.

17. The method according to claim 1, wherein the desired region is formed into a chip by the separation step.

18. The method according to claim 1, wherein the desired region is formed into a plurality of chips by the separation step.

19. The method according to claim 1, wherein the member is formed again using a remaining member that is left after the desired region is separated from the member.

20. A thin-film semiconductor device obtained by processing a member having, on a separation layer, a semiconductor film having a semiconductor element and/or semiconductor integrated circuit, wherein the process comprises

the kerf formation step of forming kerfs from the semiconductor film side of the member, and

the separation step of, after the kerf formation step, separating a desired region of the semiconductor element and/or semiconductor integrated circuit from the member.

21. A method of manufacturing a semiconductor device, comprising:

preparing a member which has a separation layer on a base and a semiconductor film having a plurality of chip regions on the separation layer;

forming kerfs in the semiconductor film to partition the plurality of chip regions; and

forming cracks in the separation layer to separate each of the partitioned chip regions from the base.

22. A semiconductor device obtained by processing a member having a separation layer on a base and a plurality of chip regions on the separation layer,

wherein the process comprises

forming kerfs in the semiconductor film to partition the plurality of chip regions, and

forming cracks in the separation layer to separate each of the partitioned chip regions from the base.