Pitch compensation in flip-chip packaging

• US 20020109238A1
• Filed: 04/17/2002
• Published: 08/15/2002
• Est. Priority Date: 04/17/2002
• Status: Active Grant

• Current Assignee: Callaway Golf Company, ASE Electronics Sendirian Berhad (Calspan Aero Systems Engineering, Inc.), Celerity Research, Pte., Ltd.
• Original Assignee: Celerity Research, Pte., Ltd.
• Inventors: Hilton, Robert M.
• Granted Patent: US 6,699,732 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16108 the bump connector not being orthogonal to the surface
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/171 Disposition
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01037 Rubidium [Rb]
• CPC Class Codes: H01L 2924/0105 Tin [Sn]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/381 : Pitch distance
• CPC Class Codes: H05K 1/111 : Pads for surface mounting, e.g. lay-out
• CPC Class Codes: H05K 2201/09427 : Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
• CPC Class Codes: H05K 2203/048 : Self-alignment during soldering; Terminals, pads or shape of solder adapted therefor
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A flip-chip package and packaging method use a substrate having bond pad spacing that matches terminal spacing on a chip at an elevated temperature, such as the temperature of the chip during bonding to the substrate, the melting point of solder used on the chip, a temperature within the range of thermal cycling of the chip, or an operating temperature of the chip. Matching spacing at an elevated temperature permits a better alignment at the bonding temperature for formation of stronger bonds.

Claims

1. A device comprising:

a chip having a plurality of terminals; and

a substrate having traces including a plurality of contact areas respectively corresponding to the plurality of terminals, wherein each terminal is electrically connected to the corresponding contact area, and wherein spacing of the contact areas on the substrate matches spacing of the terminals on the chip when the chip and substrate are at an elevated temperature.

2. The device of claim 1, wherein the elevated temperature is approximately equal to a temperature at which the terminals bond to corresponding contact areas.

3. The device of claim 1, wherein each terminal comprises a solder bump.

4. The device of claim 3, wherein the elevated temperature is approximately equal to the melting point of the solder bumps.

5. The device of claim 1 , wherein the device has an expected temperature range for thermal cycling of the chip and the elevated temperature within the expected temperature range.

6. The device of claim 5, wherein the elevated temperature is at a midpoint of the expected temperature range.

7. The device of claim 1, wherein the elevated temperature is an expected operating temperature of the chip.

8. A method for fabricating a flip-chip package, comprising:

aligning a chip with a substrate including conductive traces, wherein terminals of the chip respectively correspond to contact areas of the traces and a spacing of the terminals matches a spacing of the contact areas at an elevated temperature; and

bonding the terminals to the corresponding contact areas at a bonding temperature.

9. The method of claim 8, wherein the bonding temperature is at least as high as the elevated temperature.

10. The method of claim 8, wherein the bonding temperature is equal to the elevated temperature.

11. The method of claim 8, wherein the terminals comprise solder bumps, and the elevated and bonding temperatures are about equal to a melting temperature of the solder bumps.

12. The method of claim 8, wherein the elevated temperature is selected to minimize thermal stress on bonds between the terminals and the contact areas during thermal cycling of the flip-chip.

13. The method of claim 12, wherein the elevated temperature is about equal to a middle temperature of a temperature range expected during thermal cycling of the flip-chip package.

14. The method of claim 8, wherein the elevated temperature is about equal to an expected operating temperature of the flip-chip package.