Method and system for supporting multiple cache configurations
First Claim
1. A device, comprising:
- a processor card;
a first memory device mounted upon said processor card, said first memory device including a first address pin and a second address pin; and
a second memory device mounted upon said processor card, said second memory device including a third address pin and a fourth address pin, said first address pin and said third address pin being functionally equivalent address pins, said second address pin and said fourth address pin being functionally equivalent address pins, wherein said first address pin and said fourth address pin are electrically coupled to thereby concurrently receive a first address bit signal, and wherein said second address pin and said third address pin are electrically coupled to thereby concurrently receive a second address bit signal.
1 Assignment
0 Petitions
Accused Products
Abstract
A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.
12 Citations
27 Claims
-
1. A device, comprising:
-
a processor card;
a first memory device mounted upon said processor card, said first memory device including a first address pin and a second address pin; and
a second memory device mounted upon said processor card, said second memory device including a third address pin and a fourth address pin, said first address pin and said third address pin being functionally equivalent address pins, said second address pin and said fourth address pin being functionally equivalent address pins, wherein said first address pin and said fourth address pin are electrically coupled to thereby concurrently receive a first address bit signal, and wherein said second address pin and said third address pin are electrically coupled to thereby concurrently receive a second address bit signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A system, comprising:
-
a first memory device including a first address pin and a second address pin;
a second memory device including a third address pin and a fourth address pin, said first address pin and said third address pin being functionally equivalent address pins, said second address pin and said fourth address pin being functionally equivalent address pins; and
a microprocessor operable to concurrently provide a first address bit signal to said first address pin and said fourth address pin, said microprocessor further operable to concurrently provide a second address bit signal to said second address pin and said third address pin. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
-
-
21. A method, comprising:
-
operating a microprocessor to generate a first set of at least two address bit signals, said first set of at least two address bit signals being indicative of a first cache configuration; and
operating said microprocessor to generate a second set of at least two address bit signals, said second set of at least two address bit signals being indicative of said second cache configuration of said plurality of cache configurations. - View Dependent Claims (22, 24, 26, 27)
-
-
23. A method, comprising:
-
operating a microprocessor to select a first cache configuration of a plurality of cache configurations; and
subsequently operating said microprocessor to concurrently provide a set of at least two address bit signals to a first memory device and a second memory device, said set of at least two address bit signals being representative of said selection of said first cache configuration.
-
-
25. A method, comprising:
-
providing a processor board including a first conductor and a second conductor;
providing a first memory device including a first address pin and a second address pin;
providing a second memory device including a third address pin and a fourth address pin, said first address pin and said fourth address pin being functionally equivalent address pins, said second address pin and said third address pin being functionally equivalent address pin;
mounting said first memory device on said processor card, said first address pin contacting said first conductor, said second address pin contacting said second conductor;
mounting a second memory device said processor card, said third address pin contacting said first conductor whereby said first address pin and said third address pin are electrically coupled, said fourth address pin contacting said second conductor whereby said second address pin and said fourth address pin are electrically coupled.
-
Specification