MEMORY REDUCTION METHOD FOR A DSP-BASED GPS PROCESSOR

• US 20020113734A1
• Filed: 02/22/2001
• Published: 08/22/2002
• Est. Priority Date: 02/22/2001
• Status: Active Grant

• Current Assignee: CSR Technology Incorporated (Qualcomm, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: King, Thomas M.
• Granted Patent: US 6,583,758 B2
• Time in Patent Office: Days
• US Class Current: 342/357.13
• CPC Class Codes: G01S 19/28 Satellite selection
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain

Abstract

A method and apparatus for determining position in a GPS receiver (FIG. 4) is provided according to the invention. The apparatus includes a first switch (402), the first switch (402) receiving a digital GPS data, a first memory (409), a second memory (410) in parallel with the first memory, with the first memory and the second memory selectable by the first switch (402) for filling with the digital GPS data, and a second switch (416) selectable between the first memory (409) and the second memory (410) in order to extract the digital GPS data therefrom, wherein DSP signal processing (140) extracts digital GPS data from the first memory (409) while the second memory (410) is being filled and extracts digital GPS data from the second memory (410) while the first memory is being filled, and wherein the first memory (409) and the second memory (410) allow the digital GPS data to be processed in real time.

Claims

1. A GPS receiver data storage apparatus comprising:

a first switch, said first switch receiving a digital GPS data;

a first memory;

a second memory in parallel with said first memory, with said first memory and said second memory being selectable by said first switch for filling with said digital GPS data; and

a second switch selectable between said first memory and said second memory for extracting said digital GPS data therefrom;

wherein GPS signal processing extracts digital GPS data from said first memory while said second memory is being filled and extracts digital GPS data from said second memory while said first memory is being filled.

2. The apparatus of claim 1, wherein said first memory and said second memory allow said digital GPS data to be processed in real time.

3. The apparatus of claim 1, wherein said first switch is further connected to a source of said digital GPS data.

4. The apparatus of claim 1, wherein said second switch is further connected to a downstream digital signal processing device.

5. The apparatus of claim 1, wherein said first memory and said second memory are capable of storing a predetermined size of data.

6. The apparatus of claim 1, wherein a first memory size and a second memory store the predetermined size of digital GPS data.

7. The apparatus of claim 1, wherein a first memory size and a second memory size are dependent on a throughput of a downstream digital signal processor.

8. The apparatus of claim 1, wherein a first memory size and a second memory size are dependent on a throughput of a downstream coherent integrator device.

9. The apparatus of claim 1, wherein a downstream digital signal processor speed is inversely related to a first memory size and a second memory size.

10. A GPS receiver apparatus, comprising:

a first switch, said first switch receiving a digital GPS data;

a first memory;

a second memory in parallel with said first memory, with said first memory and said second memory being selectable by said first switch for filling with said digital GPS data;

a second switch selectable between said first memory and said second memory for extracting said digital GPS data therefrom;

a mixer connected to said second switch and further connected to a numerically controlled oscillator with said numerically controlled oscillator being provided with a predetermined Doppler characteristic, said mixer being capable of removing said predetermined Doppler characteristic from said digital GPS data;

a stack RAM connected to said mixer, said stack RAM being capable of accumulating a predetermined time interval of said digital GPS data from said mixer;

a correlator connected to said stack RAM, said correlator also receiving a predetermined Gold code, with said correlator being capable of correlating said predetermined Gold code against said digital GPS data;

a magnitude squaring block connected to said correlator, said magnitude squaring block squaring the correlation output to produce a squared integration output; and

a non-coherent integrator connected to said magnitude squaring block and capable of integrating said squared integration output to provide a pseudorange and Doppler characteristic output;

wherein GPS signal processing extracts digital GPS data from said first memory while said second memory is being filled and extracts digital GPS data from said second memory while said first memory is being filled, and wherein said first memory and said second memory allow said digital GPS data to be processed in real time;

and wherein said numerically controlled oscillator is capable of being provided with a Doppler characteristic for a selected visible GPS satellite and said correlator is capable of being provided with a corresponding Gold code for said selected visible GPS satellite to enable said apparatus to process a digital GPS data for said selected visible GPS satellite.

11. The apparatus of claim 10, wherein a correlator of said plurality of correlators is a Fast Fourier-Transform correlator.

12. The apparatus of claim 10, wherein said unique predetermined Doppler characteristic is an estimate.

13. The apparatus of claim 10, wherein said first switch is further connected to a source of said digital GPS data.

14. The apparatus of claim 10, wherein said first memory and said second memory are capable of storing a predetermined size of digital GPS data.

15. The apparatus of claim 10, wherein said first memory and said second memory both store the predetermined size of digital GPS data.

16. The apparatus of claim 10, wherein a first memory size and a second memory size are dependent on a throughput of a downstream digital signal processor.

17. The apparatus of claim 10, wherein a first memory size and a second memory size are dependent on a throughput of a downstream coherent integrator device.

18. The apparatus of claim 10, wherein a downstream digital signal processor speed is inversely related to a first memory size and a second memory size.

19. The apparatus of claim 10, wherein said mixer receives a predetermined Doppler signature for each visible GPS satellite.

20. The apparatus of claim 10, wherein said stack RAM is a dual port stack RAM.

21. The apparatus of claim 10, wherein a throughput rate of said digital signal processor is inversely proportional to the digital GPS data storage capacity of said first memory and said second memory.

22. The apparatus of claim 10, further including a results RAM capable of storing a plurality of digital GPS data for said each visible GPS satellite

24. The method of claim 23, wherein said storing is performed by a first switch capable of alternately storing said digital GPS data to said first memory and to said second memory.

25. The method of claim 23, wherein said extracting is performed by a second switch capable of alternately extracting a stored digital GPS data segment from said first memory and from said second memory.

27. The method of claim 26, wherein said storing is performed by a first switch capable of alternately storing said digital GPS data to said first memory and to said second memory.

28. The method of claim 26, wherein said extracting is performed by a second switch capable of alternately extracting a stored digital GPS data segment from said first memory and from said second memory.

29. The method of claim 26, wherein said predetermined Doppler signature is received from a base station.

30. The method of claim 26, wherein said correlating is performed by a plurality of parallel FFT correlators.

31. The method of claim 26, wherein said correlating is performed by eight parallel FFT correlators.

32. The method of claim 26, wherein said integrating is performed by a plurality of parallel non-coherent integrators.

33. The method of claim 26, wherein said integrating is performed by eight parallel non-coherent integrators.

35. The method of claim 34, wherein said initial conditions include an initial position estimate, an initial position uncertainty, a time estimate, a time uncertainty, an oscillator frequency estimate, and an oscillator frequency uncertainty.

36. The method of claim 34, wherein said method further includes a step of computing GPS satellite positions and Doppler characteristics using said initial conditions.

37. The method of claim 34, wherein said initial range estimate includes a range estimate and a Doppler search range estimate.

38. The method of claim 34, wherein said step of computing an optimum satellite search order further includes the steps of:

using a predetermined search criteria and available processing branches to find a first GPS satellite in an incoming GPS data signal;

removing a successful processing branch that found said first GPS satellite from a group of available processing branches; and

iteratively processing said incoming GPS data signal using remaining processing branches, with each successful processing branch being removed from said group of available processing branches until processing is complete.

39. The method of claim 38, wherein said predetermined search criteria is a GPS satellite elevation angle.

40. The method of claim 38, wherein said predetermined search criteria is a minimum Doppler search range.

23. A method of storing and processing a digital GPS signal in a GPS receiver having a reduced amount of memory, comprising the steps of:

storing said digital GPS signal in a first memory during a first predetermined time period;

extracting a first stored digital GPS data segment from a second memory simultaneous with said storing of said digital GPS signal in said first memory;

wherein during subsequent predetermined time periods said storing step alternates between said first memory and said second memory while said extracting step alternates between said second memory and said first memory.

26. A method of storing and processing a digital GPS signal in a GPS receiver having a reduced amount of memory, comprising the steps of:

storing said digital GPS signal in a first memory during a first predetermined time period;

extracting a first stored digital GPS data segment from a second memory simultaneous with said storing of said digital GPS signal in said first memory;

generating a predetermined Doppler signature for a subject visible satellite;

mixing said predetermined Doppler signature with said first stored digital GPS data segment to remove a Doppler characteristic from said first stored digital GPS data segment;

correlating a Gold code of said subject visible satellite to said first stored digital GPS data segment, producing a correlation output; and

integrating said correlation output to produce a pseudorange output and a Doppler output;

wherein said generating step through said mixing step are repeated for each visible satellite, and wherein during subsequent predetermined time periods said storing step alternates between said first memory and said second memory while said extracting step alternates between said second memory and said first memory.

34. A method of minimizing a GPS satellite search time in a GPS receiver having a plurality of correlation and integration satellite processing branches, comprising the steps of:

computing initial conditions that estimate a position of said GPS receiver and that estimate a GPS receiver clock accuracy;

computing an initial range estimate; and

computing an optimum satellite search order, with said optimum satellite search order computed so as to minimize a search space and minimize a search time needed to find visible GPS satellites.