Semiconductor integrated circuit device

• US 20020117722A1
• Filed: 05/05/2000
• Published: 08/29/2002
• Est. Priority Date: 05/12/1999
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Osada, Kenichi, Ikeda, Shuji, Minami, Masataka, Ishibashi, Koichiro
• Granted Patent: US 6,677,649 B2
• Time in Patent Office: Days
• US Class Current: 257/379
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/783 comprising a gate to body connection, i.e. bulk dynamic threshold voltage MOSFET for thin film transistors H01L29/78612, H01L29/78696
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.

Claims

1. A semiconductor memory device comprising a first inverter including a first N-channel metal oxide semiconductor (MOS) transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being connected to an output terminal of said first inverter and with an output terminal being connected to an input terminal of said first inverter, a third N-channel MOS transistor having a source connected to the output terminal of said first inverter and a drain connected to a first bit line and also a gate connected to a word line, and a fourth N-channel MOS transistor having a source connected to the output terminal of said second inverter and a drain connected to a second bit line plus a gate connected to a word line, wherein the first and third N-channel MOS transistors are formed in a first P-type well region, its diffusion layer having an outer shape consisting essentially of straight lines including a straight line portion with a maximal length extending parallel to a boundary relative to a first N-type well region with the first and second P-channel MOS transistors formed therein and also being linear symmetrical with respect to a straight line defined as a center line extending parallel to the boundary, and wherein the second and fourth N-channel MOS transistors are formed in a second P-type well region, its diffusion layer having an outer shape consisting essentially of straight lines including a straight line portion with a maximal length extending parallel to the boundary relative to the first n-type well region with said first and second P-channel MOS transistors formed therein and also being linear symmetrical with the straight line defined as the center line in parallel to the boundary.

2. A semiconductor memory device according to claim 1, wherein a first polycrystalline silicon lead layer for use as the gate of said third N-channel MOS transistor and a second polycrystalline silicon lead layer for use as the gate of said first P-channel MOS transistor and also as the gate of said first N-channel MOS transistor are disposed in parallel to each other, wherein a third polycrystalline silicon lead layer for use as the gate of said fourth N-channel MOS transistor and a fourth polycrystalline silicon lead layer for use as the gate of said second N-channel MOS transistor and also as the gate of said second P-channel MOS transistor are disposed in parallel to each other, and wherein the first and third polycrystalline silicon lead layers are connected via a contact to a second layer of metal lead layer constituting word lines.

3. A semiconductor memory device according to claim 1, wherein the input terminal of said first inverter and the output terminal of said second inverter are electrically connected together at a contact whereas the input terminal of said second inverter and the output terminal of said first inverter are electrically connected together at a contact.

4. A semiconductor memory device according to claim 1, wherein a power supply line connected to the first and second bit lines and the sources of said first and second P-channel MOS transistors and a ground line connected to the sources of said first and second N-channel MOS transistors are formed of a third layer of metal lead layer lying parallel to a diffusion layer.

5. A semiconductor memory device according to claim 4, wherein the first bit line formed of said third layer of metal lead layer is between a power supply line formed of said third layer of metal lead layer and a ground line as connected to the source of said first N-channel MOS transistor formed of said third layer of metal lead layer whereas the second bit line formed of said third layer of metal lead layer is between a power supply line formed of said third layer of metal lead layer and a ground line as connected to the source of said second N-channel MOS transistor formed of said third layer of metal lead layer.

6. A semiconductor memory device according to claim 1, wherein the first and second bit lines and a power supply line connected to the sources of said first and second P-channel MOS transistors are formed of a second layer of metal lead layer, wherein word lines are formed of a third layer of metal lead layer, and wherein a ground line connected to the sources of said first and second N-channel MOS transistors is formed of the third layer and second layer of metal lead layer.

7. A semiconductor memory device according to claim 1, wherein a memory cell is constituted from said first inverter and said second inverter plus said third N-channel MOS transistor as well as said fourth N-channel MOS transistor, wherein memory cells each similar in configuration to said memory cell are laid out in form of an array, and wherein contacts to a substrate of P-type well region and a contact to a substrate of N-type well region are linearly disposed within the array and at upper and lower portions of the array in a direction parallel to the word lines.

8. A semiconductor memory device according to claim 2, wherein a memory cell is constituted from said first inverter and said second inverter plus said third N-channel MOS transistor as well as said fourth N-channel MOS transistor, wherein memory cells each similar in configuration to said memory cell are laid out in form of an array, and wherein contacts to a substrate of P-type well region and a contact to a substrate of N-type well region are linearly disposed within the array and at upper and lower portions of the array in a direction parallel to the word lines.

9. A semiconductor memory device according to claim 3, wherein a memory cell is constituted from said first inverter and said second inverter plus said third N-channel MOS transistor as well as said fourth N-channel MOS transistor, wherein memory cells each similar in configuration to said memory cell are laid out in form of an array, and wherein contacts to a substrate of P-type well region and a contact to a substrate of N-type well region are linearly disposed within the array and at upper and lower portions of the array in a direction parallel to the word lines.

10. A semiconductor memory device according to claim 4, wherein a memory cell is constituted from said first inverter and said second inverter plus said third N-channel MOS transistor as well as said fourth N-channel MOS transistor, wherein memory cells each similar in configuration to said memory cell are laid out in form of an array, and wherein contacts to a substrate of P-type well region and a contact to a substrate of N-type well region are linearly disposed within the array and at upper and lower portions of the array in a direction parallel to the word lines.

11. A semiconductor memory device according to claim 5, wherein a memory cell is constituted from said first inverter and said second inverter plus said third N-channel MOS transistor as well as said fourth N-channel MOS transistor, wherein memory cells each similar in configuration to said memory cell are laid out in form of an array, and wherein contacts to a substrate of P-type well region and a contact to a substrate of N-type well region are linearly disposed within the array and at upper and lower portions of the array in a direction parallel to the word lines.

12. A semiconductor memory device according to claim 6, wherein a memory cell is constituted from said first inverter and said second inverter plus said third N-channel MOS transistor as well as said fourth N-channel MOS transistor, wherein memory cells each similar in configuration to said memory cell are laid out in form of an array, and wherein contacts to a substrate of P-type well region and a contact to a substrate of N-type well region are linearly disposed within the array and at upper and lower portions of the array in a direction parallel to the word lines.

15. A semiconductor device according to claim 14, wherein the diffusion layer formed in said N-type well region and P-type regions has its planar shape resembling a single rectangle having long sides in the elongate direction of boundary lines of said N-type well region and said first and second P-type well regions.

16. A semiconductor device according to claim 14, wherein the diffusion layer formed in said N-type well region or P-type region has its planar shape of a combined form as resulting from combination of a first rectangle having long sides in the elongate direction of boundary lines of said N-type well region and said first and second P-type well regions along with a short side of a first length and a second rectangle having long sides in the elongate direction of the boundary lines of said N-type well region and said first and second P-type well regions along with a short side of a second length, the combination being in the elongate direction of said boundary lines.

17. A semiconductor device according to claim 9, wherein

said first inverter is formed of a first N-channel MOS transistor and a first P-channel MOS transistor as formed using the first P-type well region and N-type well region,

said second inverter is formed of a second N-channel MOS transistor and a second P-channel MOS transistor as formed using the second P-type well region and N-type well region,

said first switch is formed of a third N-channel MOS transistor as formed in said first P-type well region, and

said second switch is formed of a fourth N-channel MOS transistor formed in said second P-type well region.

18. A semiconductor device according to claim 10, wherein

said first inverter is formed of a first N-channel MOS transistor and a first P-channel MOS transistor as formed using the first P-type well region and N-type well region,

said second inverter is formed of a second N-channel MOS transistor and a second P-channel MOS transistor as formed using the second P-type well region and N-type well region,

said first switch is formed of a third N-channel MOS transistor as formed in said first P-type well region, and

said second switch is formed of a fourth N-channel MOS transistor formed in said second P-type well region.

19. A semiconductor device according to claim 11, wherein

said first inverter is formed of a first N-channel MOS transistor and a first P-channel MOS transistor as formed using the first P-type well region and N-type well region,

said second inverter is formed of a second N-channel MOS transistor and a second P-channel MOS transistor as formed using the second P-type well region and N-type well region,

said first switch is formed of a third N-channel MOS transistor as formed in said first P-type well region, and

said second switch is formed of a fourth N-channel MOS transistor formed in said second P-type well region.

20. A semiconductor device according to claim 17, wherein the first and second inverters and the first and second switches constitute a static memory cell, wherein a plurality of memory cells each similar in structure to said static memory cell are provided to constitute a memory array, and wherein

bit lines are disposed parallel to an elongate direction of more than one boundary line of said N-type well region and said first and second P-type well regions whereas word lines are disposed in a direction perpendicular to the boundary line.

21. A semiconductor device according to claim 18, wherein the first and second inverters and the first and second switches constitute a static memory cell, wherein a plurality of memory cells each similar in structure to said static memory cell are provided to constitute a memory array, and wherein

bit lines are disposed parallel to an elongate direction of more than one boundary line of said N-type well region and said first and second P-type well regions whereas word lines are disposed in a direction perpendicular to the boundary line.

22. A semiconductor device according to claim 19, wherein the first and second inverters and the first and second switches constitute a static memory cell, wherein a plurality of memory cells each similar in structure to said static memory cell are provided to constitute a memory array, and wherein

bit lines are disposed parallel to an elongate direction of more than one boundary line of said N-type well region and said first and second P-type well regions whereas word lines are disposed in a direction perpendicular to the boundary line.

23. A semiconductor memory device according to claim 20, wherein said device further comprises a plurality of memory arrays each similar in structure to said memory array, and an intermediate region between said memory arrays for causing at least one of a contact to a substrate of P-type well region and a contact to a substrate of N-type well region to be disposed therein.

24. A semiconductor memory device according to claim 21, wherein said device further comprises a plurality of memory arrays each similar in structure to said memory array, and an intermediate region between said memory arrays for causing at least one of a contact to a substrate of P-type well region and a contact to a substrate of N-type well region to be disposed therein.

25. A semiconductor memory device according to claim 22, wherein said device further comprises a plurality of memory arrays each similar in structure to said memory array, and an intermediate region between said memory arrays for causing at least one of a contact to a substrate of P-type well region and a contact to a substrate of N-type well region to be disposed therein.

26. A semiconductor device according to claim 23, wherein an electrical lead having a specified voltage potential is disposed within said intermediate region in parallel to said word lines, and wherein said contact is for electrical connection between the lead and the substrate.

27. A semiconductor device according to claim 24, wherein an electrical lead having a specified voltage potential is disposed within said intermediate region in parallel to said word lines, and wherein said contact is for electrical connection between the lead and the substrate.

28. A semiconductor device according to claim 25, wherein an electrical lead having a specified voltage potential is disposed within said intermediate region in parallel to said word lines, and wherein said contact is for electrical connection between the lead and the substrate.

13. A semiconductor memory device comprising:

a first inverter having a first N-channel MOS transistor and a first P-channel MOS transistor;

a second inverter having a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being connected to an output terminal of said first inverter and with an output terminal being connected to an input terminal of said first inverter;

a third N-channel MOS transistor having a source connected to the output terminal of said first inverter, a drain connected to a first bit line, and a gate connected to a word line; and

a fourth N-channel MOS transistor having a source connected to the output terminal of said second inverter, a drain connected to a second bit line, and a gate connected to a word line,

wherein the first and third N-channel MOS transistors are formed in a first P-type well region, a diffusion layer formed in said first P-type well region has a shape as resulting from letting a rectangle having long sides in a direction parallel to a boundary relative to a first N-type well region with the first and second P-channel MOS transistors formed therein be connected in the parallel direction, the second and fourth N-channel MOS transistors are formed in a second P-type well region, and a diffusion layer formed in said second P-type well region has a shape as resulting from letting a rectangle having long sides in a direction parallel to the boundary relative to the first n-type well region with said first and second P-channel MOS transistors formed therein be connected in the parallel direction.

14. A semiconductor device comprising first and second inverters with an output of each inverter being as an input of a remaining inverter, a first switch connected to a connection node between an output of the first inverter and an input of the second inverter, and a second switch connected to a connection node between an input of said first inverter and an output of said second inverter, wherein

said semiconductor device has an N-type well region and first and second P-type well regions as disposed on opposite sides of said N-type well region,

a diffusion layer formed in each of said N-type well region and said first and second P-type well regions is arranged in planar shape to have one of (1) a shape consisting essentially of a single rectangle having long sides in an elongate direction of a boundary line of said N-type well region and said first and second P-type well regions and (2) a shape resulting from combination of a plurality of rectangles in the elongate direction of the boundary line of said N-type well region and said first and second P-well regions, the rectangles having long sides in said elongate direction.

29. A semiconductor memory device comprising:

a plurality of memory arrays each including an array of memory cells each having at least a pair of N-type well region and P-type well region;

at least one intermediate region between the memory arrays;

said N-type well region and P-type well region defining therebetween a boundary with at least one straight line portion;

a diffusion layer formed in each of said P-type well region and P-type well region to have a planar shape of one of (1) a shape of rectangle having long sides extending parallel to said straight line portion and (2) a shape resulting from letting a plurality of rectangles having long sides extending parallel to said straight line portion be combined together via respective short sides thereof;

bit lines disposed parallel to said straight line portion along with word lines disposed in a direction perpendicular to said straight line portion; and

said intermediate region including at least one type of power supply lead as disposed therein and extending in the direction perpendicular to said straight line portion and also a lead formed therein for electrical contact between the power supply lead and the diffusion layer as formed in said N-type well region or P-type well region.