Low fabrication cost, fine pitch and high reliability solder bump

• US 20020121692A1
• Filed: 03/05/2001
• Published: 09/05/2002
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung, Lee, Jin-Yuan, Huang, Ching-Cheng
• Granted Patent: US 6,818,545 B2
• Time in Patent Office: Days
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/11849 Reflowing
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13017 being non uniform along the bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13083 Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Claims

1. A method for forming a metal bump on a semiconductor surface, comprising the steps of:

providing a semiconductor surface;

providing a contact pad over said semiconductor surface, having a layer of passivation formed thereover with an opening to said contact pad;

a barrier layer is deposited over the surface of the layer of passivation and in the opening;

depositing a layer of photoresist over the barrier layer;

forming a pillar opening in said photoresist that aligns with the contact pad;

depositing a layer of pillar metal in said pillar opening;

depositing a layer of under bump metal over said pillar metal;

depositing a layer of solder metal over said under bump metal;

removing the layer of photoresist;

reducing the diameter of the layer of pillar metal;

etching the barrier layer; and

reflowing the solder metal to form said metal bump.

2. The method of claim 1 wherein said barrier layer comprises titanium applied to a thickness of between about 500 and 2000 Angstrom and more preferably to a thickness of about 1000 Angstrom.

3. The method of claim 1 wherein said layer of photoresist applied to a thickness of between about 100 and 200 μ

m and more preferably to a thickness of about 150 μ

m.

4. The method of claim 1 wherein said layer of pillar metal comprises copper applied to a thickness of between about 10 and 100 μ

m and more preferably to a thickness of about 50 μ

m.

5. The method of claim 1 wherein said layer of under bump metal comprises nickel applied to a thickness of between about 1 and 10 μ

m and more preferably to a thickness of about 4 μ

m.

6. The method of claim 1 wherein said layer of solder metal comprises solder applied to a thickness of between about 30 and 100 μ

m and more preferably to a thickness of about 50 μ

m.

35. The method of claim 1 wherein said reducing the diameter of the layer of pillar metal comprises reducing the diameter by more than 0.2 μ

m.

36. The method of claim 1, further comprising an additional step of thermally oxidizing said under bump metal and said pillar metal, said additional step to be performed prior to said reflowing the solder metal to form said metal bump.

43. The method of claim 1 with the addition of the deposition of a seed layer over said barrier layer, said seed layer being deposited after said barrier layer is deposited over the surface of the layer of passivation and in the opening.

7. A metal bump contact, comprising:

a semiconductor surface;

a layer of dielectric over said semiconductor surface;

a contact pad over said layer of dielectric, formed of a first material;

a layer of passivation over said layer of dielectric, having an opening therein aligned with said contact pad;

a barrier layer deposited over said layer of dielectric, including said opening created in said layer of passivation;

a stack of three metal layers, aligned with the contact pad and having an equal diameter that is about equal to the surface area of the contact pad, starting with a layer in contact with the barrier layer, of a layer of pillar metal, a layer of under bump metal and a layer of solder metal;

the diameter of the pillar metal has been reduced by a measurable amount;

the barrier layer has been removed using either isotropic or anisotropic methods of etching; and

the solder metal being reflowed.

8. The metal bump contact of claim 7 wherein said barrier layer comprises titanium or copper applied to a thickness of between about 500 and 2000 Angstrom and more preferably to a thickness of about 1000 Angstrom.

9. The metal bump contact of claim 7 wherein said layer of photoresist applied to a thickness of between about 100 and 200 μ

m and more preferably to a thickness of about 150 μ

m.

10. The metal bump contact of claim 7 wherein said layer of pillar metal comprises copper applied to a thickness of between about 10 and 100 μ

m and more preferably to a thickness of about 50 μ

m.

11. The metal bump contact of claim 7 wherein said layer of under bump metal comprises nickel applied to a thickness of between about 1 and 10 μ

m and more preferably to a thickness of about 4 μ

m.

12. The metal bump contact of claim 7 wherein said layer of solder metal comprises solder applied to a thickness of between about 30 and 100 μ

m and more preferably to a thickness of about 50 μ

m.

14. The method of claim 13 wherein said barrier layer comprises titanium or copper applied to a thickness of between about 500 and 2000 Angstrom and more preferably to a thickness of about 1000 Angstrom.

15. The method of claim 13 wherein said layer of photoresist applied to a thickness of between about 100 and 200 μ

m and more preferably to a thickness of about 150 μ

m.

16. The method of claim 13 wherein said layer of pillar metal comprises copper applied to a thickness of between about 10 and 100 μ

m and more preferably to a thickness of about 50 μ

m.

17. The method of claim 13 wherein said layer of under bump metal comprises nickel applied to a thickness of between about 1 and 10 μ

m and more preferably to a thickness of about 4 μ

m.

18. The method of claim 13 wherein said layer of solder metal comprises solder applied to a thickness of between about 30 and 100 μ

m and more preferably to a thickness of about 50 μ

m.

19. The method of claim 13 further comprising performing an in-situ sputter clean of the exposed surface of the barrier layer, said additional step to be performed prior to said depositing a layer of pillar metal.

20. The method of claim 13 wherein said material that blocks metal depositing comprises photoresist.

37. The metal bump contact of claim 7 wherein said diameter of the pillar metal has been reduced by a measurable amount comprises reducing the diameter by more than 0.2 μ

m.

38. The metal bump contact of claim 7, further said under bump metal and said pillar metal having been oxidized prior to said the solder metal being reflowed.

39. The method of claim 13 wherein said reducing the diameter of the pillar metal by a measurable amount comprises reducing the diameter by more than 0.2 μ

m.

40. The method of claim 13, further comprising an additional step of thermally oxidizing said under bump metal and said pillar metal, said additional step to be performed prior to said reflowing the solder metal, forming the metal bump.

44. The metal bump contact of claim 7 with a seed layer deposited over said barrier layer.

45. The method of claim 13 with the addition of depositing a seed layer over the surface of said barrier layer, said seed layer being deposited after depositing a layer of barrier material over the surface of said layer of passivation.

13. A method for forming a metal bump on a semiconductor surface, comprising the steps of:

providing a semiconductor surface, providing a contact pad over said semiconductor surface, having a layer of passivation formed thereover with an opening to said contact pad;

depositing a layer of barrier material over the surface of said layer of passivation, including the opening created in said layer of passivation;

depositing a layer of material that blocks metal depositing over the surface of the barrier layer;

patterning and etching the layer of material that blocks metal depositing, creating an opening in the layer of material that blocks metal depositing that aligns with the contact pad, having a diameter about equal to the surface of the contact pad, partially exposing the surface of the barrier layer over a surface area that aligns with the contact pad, then;

depositing a layer of pillar metal over the exposed surface of the barrier layer, then;

depositing a layer of Under Bump Metallurgy (UBM) over the surface of the layer of pillar metal, then;

depositing a layer of bump metal over the surface of the layer of UBM;

removing the layer of material that blocks metal depositing from above the surface of the barrier layer;

etching the layer of pillar metal, reducing the diameter of the pillar material by a measurable amount;

removing said barrier layer from the surface of said layer of passivation, using either isotropic or anisotropic methods of etching; and

reflowing said solder metal, forming the metal bump.

21. A method for forming a metal bump on a semiconductor surface, comprising the steps of:

providing a semiconductor surface, said semiconductor surface having been provided in or on the surface thereof with a contact pad, said contact pad sitting on an underlying layer of dielectric and being in electrical contact with at least one point of electrical contact in or on the surface of said substrate;

providing a base layer for said metal bump, said base layer having a barrier layer as a surface layer; and

providing a column for said metal bump, said column for said metal bump comprising three successive layers of pillar metal, under bump metal and solder metal; and

providing said metal bump.

22. The method of claim 21 wherein said providing a base layer for said metal bump comprises the steps of:

depositing a layer of passivation over the surface of said layer of dielectric underlying the contact pad, including the surface of said contact pad;

patterning and etching said layer of passivation, creating an opening in said layer of passivation, partially exposing the surface of said contact pad, said opening created in said layer of passivation being smaller than a surface area of said contact pad by a measurable amount; and

depositing a layer of barrier material over the surface of said layer of passivation, including the opening created in said layer of passivation

23. The method of claim 21 wherein said providing a column for said metal bump comprises the steps of:

depositing a layer of material that blocks metal depositing over the surface of the barrier layer;

patterning and etching the layer of material that blocks metal depositing, creating an opening in the layer of material that blocks metal depositing that aligns with the contact pad, having a diameter about equal to the surface of the contact pad, partially exposing the surface of the barrier layer over a surface area that aligns with the contact pad, then;

depositing a layer of pillar metal over the exposed surface of the barrier layer, then;

depositing a layer of Under Bump Metallurgy (UBM) over the surface of the layer of pillar metal, then;

depositing a layer of bump metal over the surface of the layer of UBM;

removing the layer of material that blocks metal depositing from above the surface of the barrier layer;

etching the layer of pillar metal, reducing the diameter of the pillar metal by a measurable amount; and

removing said barrier layer from the surface of said layer of passivation, using either isotropic or anisotropic methods of etching.

24. The method of claim 21 wherein providing said metal bump comprises reflowing said solder metal, forming the metal bump.

25. The method of claim 21 wherein said barrier layer comprises titanium or copper applied to a thickness of between about 500 and 2000 Angstrom and more preferably to a thickness of about 1000 Angstrom.

26. The method of claim 21 wherein said layer of photoresist applied to a thickness of between about 100 and 200 μ

m and more preferably to a thickness of about 150 μ

m.

27. The method of claim 21 wherein said layer of pillar metal comprises copper applied to a thickness of between about 10 and 100 μ

m and more preferably to a thickness of about 50 μ

m.

28. The method of claim 21 wherein said layer of under bump metal comprises nickel applied to a thickness of between about 1 and 10 μ

m and more preferably to a thickness of about 4 μ

m.

29. The method of claim 21 wherein said layer of solder metal comprises solder applied to a thickness of between about 30 and 100 μ

m and more preferably to a thickness of about 50 μ

m.

30. The method of claim 21 wherein said semiconductor surface is selected from the group of surfaces consisting of semiconductor substrates, printed circuit boards, flex circuits, metallized substrates, glass substrates and semiconductor device mounting support.

31. The method of claim 30 wherein said semiconductor substrate is selected from the group of substrates consisting of semiconductor substrates, ceramic substrates, glass substrates, gallium arsenide substrates, silicon on insulator (SOI) substrates and silicon on sapphire (SOS) substrates.

32. The method of claim 21 wherein said contact pad comprises aluminum or copper or a compound thereof.

33. The method of claim 23 further comprising performing an in-situ sputter clean of the exposed surfaces of the barrier layer, said additional step to be performed prior to said depositing a layer of pillar metal.

34. The method of claim 23 wherein said material that blocks metal depositing comprises photoresist.

41. The method of claim 23 wherein said reducing the diameter of the pillar metal by a measurable amount comprises reducing the diameter by more than 0.2 μ

m.

42. The method of claim 24, further comprising an additional step of thermally oxidizing said under bump metal and said pillar metal, said additional step to be performed prior to said reflowing the solder metal, forming the metal bump.

46. The method of claim 22 with an additional step of depositing a seed layer over the surface of said barrier layer, said seed layer being deposited after depositing a layer of barrier material over the surface of said layer of passivation.