Method of forming an insulating layer in a trench isolation type semiconductor device

• US 20020123206A1
• Filed: 11/26/2001
• Published: 09/05/2002
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Heo, Jin-Hwa, Hong, Soo-Jin, Goo, Ju-Seon, Kim, Hong-Gun, Hong, Eun-Kee, Park, Moon-Han
• Granted Patent: US 6,566,229 B2
• Time in Patent Office: Days
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264

Abstract

A method of forming a trench-type device isolation layer in which a trench is filled through two steps, wherein a polysilazane solution is coated on a semiconductor substrate, in which a trench for device isolation layer is formed, in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of the trench. In order to maintain a conformal coating thickness without overfilling the trench, the polysilazane solution preferably has a solid-state perhydro polysilazane ([SiH₂NH]n) of between about 5 to about 15 percent by weight. Following formation of the SOG layer, a subsequent annealing process is carried out. The SOG layer is etched to make a top surface of the remaining SOG layer recessed down to a degree of about 1000 Å from an inlet of the trench, and a remaining space of the trench is filled with an ozone TEOS USG layer or an HDP CVD layer.

Claims

1. A method of forming a trench-type device isolation layer, comprising:

coating a polysilazane solution on a semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling a predetermined portion of a trench formed in the semiconductor substrate for device isolation;

annealing the SOG layer until an upper portion of the SOG layer is changed to a silicon oxide layer; and

stacking a CVD type silicon oxide layer on the SOG layer to fill a remaining space of the trench.

2. A method of forming a trench-type device isolation layer, comprising:

coating a polysilazane solution on a semiconductor substrate in a spin on glass (SOG) manner to form an SOG layer filling a trench formed in the semiconductor substrate for device isolation;

performing a thermal process for changing an upper portion of the SOG layer to a silicon oxide layer;

etching the thermally treated SOG layer to form a remaining SOG layer filling a predetermined portion of the trench; and

stacking a CVD type silicon oxide layer on the remaining SOG layer to fill a remaining portion of the trench.

3. The method as claimed in claim 2, wherein a solid ingredient of the polysilazane solution is between about 5 to about 20 percent by weight, and the SOG layer is coated on an active region around the trench to a thickness of about 500 Å

or less.

4. The method as claimed in claim 2, wherein the subsequent thermal process consists of a bake process and an annealing process that is performed in a steam (H₂O)-supplied oxidation ambient at a temperature of between about 700°

C. to about 800°

C. for between about 10 to about 60 minutes.

5. The method as claimed in claim 2, wherein the SOG layer is etched to make a top surface of the remaining SOG layer recessed from a top surface of the semiconductor substrate by about 1000 Å

.

6. The method as claimed in claim 2, wherein the polysilazane solution contains only a solid-state perhydro polysilazane ([SiH₂NH]n) of between about 5 to about 15 percent by weight.

7. The method as claimed in claim 2, wherein the CVD type silicon oxide layer is formed using a high density plasma (HDP)CVD.

8. The method as claimed in claim 7, further comprising planarizing the silicon oxide layer in a chemical mechanical polishing (CMP) manner after the formation thereof.

9. The method as claimed in claim 2, wherein the subsequent process includes a bake process and an annealing process that is performed in a steam (H₂O) and a nitrogen (N₂)-supplied oxidation ambient at a temperature of between about 700°

C. to about 800°

C. for between about 10 to about 60 minutes.