Scalable multiprocessor system and cache coherence method implementing store-conditional memory transactions while an associated directory entry is encoded as a coarse bit vector
First Claim
1. A multiprocessor computer system including a plurality of nodes, each node including:
- an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory;
a memory cache for caching a multiplicity of memory lines of information, including memory lines of information stored in a remote memory subsystem that is local to another node;
a protocol engine implementing a negative acknowledgment free cache coherence protocol, the protocol engine including a memory transaction array for storing an entry related to a memory transaction, the entry including a memory transaction state, the memory transaction concerning a memory line of information; and
logic for processing the memory transaction, including advancing the memory transaction when predefined criteria are satisfied and storing a state of the memory transaction in the memory transaction array;
wherein the protocol engine is configured to support a store-conditional memory transaction initiated by a requesting node for exclusive ownership of an identified memory line of information stored in the remote memory subsystem that is local to a first node in the plurality of nodes, and wherein the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is exclusive owner of the memory line of information;
the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is sharing the memory line of information;
the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node ambiguously indicates that the requesting node is sharing the memory line of information and the requesting node is in fact sharing the memory line of information; and
the store-conditional memory transaction fails if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is not sharing the memory line of information.
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Accused Products
Abstract
A system including a plurality of processor nodes is configured to execute a cache coherence protocol that avoids the use of negative acknowledgments and ordering requirements on the underlying transaction-message interconnect/network, and implements store-conditional memory transactions. A store-conditional memory transaction succeeds if a directory tracking the state of a memory line of information unambiguously indicates that the requesting node is the exclusive owner of the memory line, if the directory ambiguously indicates that the requesting node is sharing the memory line and the requesting node is in fact sharing the memory line, or if the directory unambiguously indicates that the requesting node is sharing the memory line. The store-conditional memory transaction fails if the directory unambiguously indicates that the requesting node is not sharing the memory line, or if the directory ambiguously indicates that the requesting node may be sharing the memory line and the requesting node is in fact not sharing the memory line.
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Citations
49 Claims
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1. A multiprocessor computer system including a plurality of nodes, each node including:
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an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory;
a memory cache for caching a multiplicity of memory lines of information, including memory lines of information stored in a remote memory subsystem that is local to another node;
a protocol engine implementing a negative acknowledgment free cache coherence protocol, the protocol engine including a memory transaction array for storing an entry related to a memory transaction, the entry including a memory transaction state, the memory transaction concerning a memory line of information; and
logic for processing the memory transaction, including advancing the memory transaction when predefined criteria are satisfied and storing a state of the memory transaction in the memory transaction array;
wherein the protocol engine is configured to support a store-conditional memory transaction initiated by a requesting node for exclusive ownership of an identified memory line of information stored in the remote memory subsystem that is local to a first node in the plurality of nodes, and wherein the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is exclusive owner of the memory line of information;
the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is sharing the memory line of information;
the store-conditional memory transaction succeeds if the directory in the memory subsystem local to the first node ambiguously indicates that the requesting node is sharing the memory line of information and the requesting node is in fact sharing the memory line of information; and
the store-conditional memory transaction fails if the directory in the memory subsystem local to the first node unambiguously indicates that the requesting node is not sharing the memory line of information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31, 32, 33, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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25. A multiprocessor computer system including a plurality of nodes, each node including
an interface to a local memory subsystem, the local memory subsystem storing a multiplicity of memory lines of information and a directory; -
a memory cache for caching a multiplicity of memory lines of information, including memory lines of information stored in a remote memory subsystem that is local to another node;
a protocol engine implementing a negative acknowledgment free cache coherence protocol, the protocol engine including a memory transaction array for storing an entry related to a memory transaction, the entry including a memory transaction state, the memory transaction concerning a memory line;
logic for processing the memory transaction, including advancing the memory transaction when predefined criteria are satisfied and storing a state of the memory transaction in the memory transaction array;
the protocol engine configured to support a store-conditional memory transaction, wherein the protocol engine included in a requesting node from the plurality of nodes sends a store-conditional request to a first node from the plurality of nodes, said store-conditional request identifying a memory line of information stored in the remote memory subsystem that is local to the first node;
the protocol engine included in the first node sends a may-succeed reply to the requesting node in response to the store-conditional request if the directory in the memory subsystem local to the first node ambiguously indicates that the requesting node is sharing the memory line of information;
the protocol engine included in the requesting node sends a first responsive protocol message to the first node in response to the may-succeed reply if the requesting node is sharing the memory line of information; and
the protocol engine included in the first node modifies a directory entry, in the directory in the memory subsystem local to the first node, corresponding to the memory line of information to indicate that the requesting node is exclusive owner of the memory line of information in response to the first responsive protocol message.
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Specification