Automatic substrate biasing circuit

• US 20020125934A1
• Filed: 01/16/2002
• Published: 09/12/2002
• Est. Priority Date: 01/16/2001
• Status: Abandoned Application

• Current Assignee: Elan Microelectronics Corporation
• Original Assignee: Elan Microelectronics Corporation
• Inventors: Chiang, Sheng-Shiang, Wu, Kap-Pin
• Application Number:
  US10/053,281
• Publication Number:
  US 20020125934A1
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146

Abstract

An automatic substrate biasing circuit, which detects the voltage source having the largest magnitude of voltage in the circuit, to bias the substrate voltage of the circuit to a desired level automatically based on the comparison result. A comparator is used in the present invention to compare different voltage sources to obtain a comparison result, which is subsequently received by a control circuit to selectively choose one of the voltage sources to control the switching operation of the switch, so that the largest voltage of the circuit can be obtained. This voltage is then used to bias the substrate voltage to a desired level.

Claims

1. An automatic substrate biasing circuit for use in integrated circuit devices to bias a substrate voltage to a desired level, comprising:

a comparator, which compares a plurality of voltage sources to generate a comparison signal;

a shift control circuit, which generates a plurality of control signals corresponding to the voltage sources according to the comparison signal; and

a switching circuit, which selectively determines one of the voltage sources as the substrate voltage according to the control signals;

wherein the substrate voltage is coupled to the shift control circuit to supply power to the shift control circuit.

2. The automatic substrate biasing circuit as claimed in claim 1, wherein the comparator comprises:

a first PMOS transistor having a gate, source, base and drain, wherein the source and the base of the first PMOS transistor are jointly coupled to a first voltage source, the gate of the first PMOS transistor is coupled to the drain of the first PMOS transistor;

a second PMOS transistor having a gate, source, base and drain, wherein the source and the base of the second PMOS transistor are jointly coupled to a second voltage source, the gate of the second PMOS transistor is coupled to the gate of the first PMOS transistor, the comparison signal is generated from the drain of the second PMOS transistor;

a first NMOS transistor having a gate, source, and drain, wherein the drain and the gate of the first NMOS transistor are jointly coupled to the drain of the first PMOS transistor, the source of the first NMOS transistor is coupled to a ground voltage; and

a second NMOS transistor having a gate, source, and drain, wherein the drain of the second NMOS transistor is coupled to the drain of the second PMOS transistor, the gate of the second NMOS transistor is coupled to the gate of the first NMOS transistor, and the source of the second NMOS transistor is coupled to the ground voltage.

3. The automatic substrate biasing circuit as claimed in claim 1, wherein the comparator comprises:

a current source for generating a reference current;

a first PMOS transistor having a gate, source, base and drain, wherein the source and the base of the first PMOS transistor are jointly coupled to a first voltage source, the gate of the first PMOS transistor is coupled to the drain of the first PMOS transistor;

a second PMOS transistor having a gate, source, base and drain, wherein the source and the base of the second PMOS transistor are coupled to a second voltage source, the gate of the second PMOS transistor is coupled to the gate of the first PMOS transistor, and the comparison signal is generated from the drain of the second PMOS transistor;

a first NMOS transistor having a gate, source, and drain, wherein the drain and the gate of the first NMOS transistor are coupled to the current source, the source of the first NMOS transistor is coupled to the ground voltage;

a second NMOS transistor having a gate, source, and drain, wherein the drain of the second NMOS transistor is coupled to the drain of the first PMOS transistor, the gate of the second NMOS transistor is coupled to the gate of the first NMOS transistor, and the source of the second NMOS transistor is coupled to the ground voltage; and

a third NMOS transistor having a gate, source, and drain, wherein the drain of the third NMOS transistor is coupled to the drain of the second PMOS transistor, the gate of the third NMOS transistor is coupled to the gate of the first NMOS transistor, and the source of the third NMOS transistor is coupled to the ground voltage.

4. The automatic substrate biasing circuit as claimed in claim 1, wherein the shift control circuit comprises:

a first inverter for receiving the comparison signal and the substrate voltage signal to generate a first inverting signal;

a second inverter for receiving the first inverting signal and the substrate voltage signal to generate a first control signal; and

a third inverter for receiving the first control signal and the substrate voltage signal to generate a second control signal.

5. The automatic substrate biasing circuit as claimed in claim 1, wherein the first inverter comprises a Smith trigger circuit.

6. The automatic substrate biasing circuit as claimed in claim 1, wherein the shift control circuit comprises:

a third PMOS transistor having a gate, source, and drain, wherein the source of the third PMOS transistor is coupled to the substrate voltage signal, the first control signal is generated from the drain of the third PMOS transistor, and the second control signal is generated from the gate of the third PMOS transistor;

a fourth PMOS transistor having a gate, source, and drain, wherein the source of the fourth PMOS transistor is coupled to the substrate voltage signal, the drain of the fourth PMOS transistor is coupled to the gate of the third PMOS transistor, and the gate of the fourth PMOS transistor is coupled to the drain of the third PMOS transistor;

a third NMOS transistor having a gate, source, and drain, wherein the drain of the third NMOS transistor is coupled to the drain of the third PMOS transistor, the gate of the third NMOS transistor receives the comparison signal, and the source of the third NMOS transistor is coupled to the ground voltage;

a fourth inverter for receiving the comparison signal to generate a fourth inverting signal; and

a fourth NMOS transistor having a gate, source, and drain, wherein the drain of the fourth NMOS transistor is coupled to the drain of the fourth PMOS transistor, the gate of the fourth NMOS transistor receives the fourth inverting signal, and the source of the fourth NMOS transistor is coupled to the ground voltage.

7. The automatic substrate biasing circuit as claimed in claim 1, wherein the switching circuit comprises:

a fifth PMOS transistor having a gate, source, base and drain, wherein the gate of the fifth PMOS transistor receives the first control signal, the source and the base of the fifth PMOS transistor are jointly coupled to the substrate voltage signal, and the drain of the fifth PMOS transistor is coupled to the first voltage source; and

a sixth PMOS transistor having a gate, source, base and drain, wherein the gate of the sixth PMOS transistor receives the second control signal, the source and the base of the sixth PMOS transistor are jointly coupled to the substrate voltage signal, and the drain of the sixth PMOS transistor is coupled to the second voltage source.