Method of forming a multilayer dielectric stack

• US 20020130340A1
• Filed: 04/30/2002
• Published: 09/19/2002
• Est. Priority Date: 02/11/2000
• Status: Active Grant

• Current Assignee: Yanjun Ma, Yoshi Ono
• Original Assignee: Yanjun Ma, Yoshi Ono
• Inventors: Ma, Yanjun, Ono, Yoshi
• Granted Patent: US 6,627,503 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66583 with initial gate mask or masking layer complementary to the prospective gate location, e.g. with dummy source and drain contacts

Abstract

A multilayer dielectric stack is provided which has alternating layers of a high-k material and an interposing material. The presence of the interposing material and the thinness of the high-k material layers reduces or eliminate effects of crystallization within the high-k material, even at relatively high annealing temperatures. The high-k dielectric layers are a metal oxide of preferably zirconium or hafnium. The interposing layers are preferably amorphous aluminum oxide, aluminum nitride, or silicon nitride. Because the layers reduce the effects of crystalline structures within individual layers, the overall tunneling current is reduced. Also provided are atomic layer deposition, sputtering, and evaporation as methods of depositing desired materials for forming the above-mentioned multilayer dielectric stack.

Claims

1. A MOS transistor comprising:

a) a gate electrode;

b) a channel region having a top surface underlying the gate electrode; and

c) a gate dielectric stack, which comprises a first dielectric layer comprising a first dielectric material, a second dielectric layer comprising a second dielectric material, and a third dielectric layer comprising the first dielectric material, interposed between the gate electrode and the channel region top surface.

2. An integrated circuit (IC) structure for an IC comprising a multilayer dielectric stack comprising:

a) a first dielectric layer comprising a first dielectric material overlying a semiconductor substrate;

b) a second dielectric layer comprising a second dielectric material overlying the first layer;

c) a third dielectric layer comprising the first dielectric material overlying the first and second dielectric layers; and

d) an electrode overlying the dielectric stack.

3. The integrated circuit structure as in claim 2, wherein the first dielectric material is selected from the group consisting of ZrO₂, HfO₂, TiO₂, and Ta₂O₅, and the second dielectric material is selected from the group consisting of Al₂O₃, AlN, SiN, Si₃N₄ and SiO₂.

4. The integrated circuit structure as in claim 2, wherein the first dielectric material is selected from the group consisting of ZrO₂, and HfO₂, and the second dielectric material is selected from the group consisting of Al₂O₃, AlN, SiN and Si₃N₄.

5. The integrated circuit structure as in claim 2, wherein the first dielectric material is selected from the group consisting of Al₂O₃, AlN, SiN, Si₃N₄and SiO₂, and the second dielectric material is selected from the group consisting of ZrO₂, HfO₂, TiO₂, and Ta₂O₅.

6. The integrated circuit structure as in claim 2, wherein the first dielectric layer is less than 50 angstroms thick.

7. The integrated circuit structure as in claim 2, wherein the first dielectric layer is between approximately 2 and 5 angstroms thick.

8. The integrated circuit structure as in claim 2, wherein the second dielectric layer is less than 50 angstroms thick.

9. The integrated circuit structure as in claim 2, wherein the second dielectric layer is between approximately 2 and 5 angstroms thick.

10. The integrated circuit structure as in claim 2, further comprising an oxidation barrier interposed between the first dielectric layer and the semiconductor substrate.

11. The integrated circuit structure as in claim 10, wherein the oxidation barrier is composed of material selected from the group consisting of silicon nitride and silicon oxynitride.

12. The integrated circuit structure as in claim 2, wherein a plurality of alternating layers of the first dielectric material and the second dielectric material are interposed between the semiconductor substrate and the electrode.

13. The integrated circuit structure as in claim 12, wherein the plurality of alternating layers has a combined thickness of between approximately 20 and 200 angstroms thick.

15. The method of claim 14, further comprising the step of annealing the semiconductor substrate at a temperature between approximately 400 and 900 degrees Celsius, whereby the dielectric stack is conditioned.

16. The method of claim 15, further comprising the step of depositing an electrode layer over the dielectric stack and the step of patterning the electrode layer and underlying dielectric stack to form a desired integrated circuit structure.

17. The method of claim 14, wherein the step of forming the first dielectric layer uses atomic layer deposition to deposit a layer of the first dielectric material.

18. The method of claim 17, wherein the step of forming the second dielectric layer uses atomic layer deposition to deposit a layer of the second dielectric material.

19. The method of claim 14, wherein the step of forming the first dielectric layer uses atomic layer deposition to deposit of a first precursor of the first dielectric material.

20. The method of claim 19, further comprising the step of oxidizing the first precursor to form the first dielectric material.

21. The method of claim 19, wherein the first precursor is deposited as a self-limiting monolayer.

22. The method of claim 19, wherein the first precursor is selected from the group consisting of ZrCl₄, Zr(iOPr)₄and Zr(tmhd)₄.

23. The method of claim 14, wherein the step of forming the first dielectric layer uses sputtering of a first target for a predetermined duration and the step of forming the second dielectric layer uses pulsed sputtering of a second target for a predetermined duration.

24. The method of claim 23, wherein the duration of sputtering the first target and the second target is controlled by shutters.

25. The method of claim 23, wherein sputtering is performed in an oxidizing atmosphere.

26. The method of claim 14, wherein the step of forming the first dielectric layer uses evaporation of a first target for a predetermined duration and the step of forming the second dielectric layer uses evaporation of a second target for a predetermined duration.

27. The method of claim 26, wherein the duration of evaporation of the first target and the second target is controlled by shutters.

14. A method of forming a dielectric stack comprising the steps of:

a) forming a first dielectric layer on an upper surface of a semiconductor substrate;

b) forming a second dielectric layer on the first dielectric layer; and

c) forming a third dielectric layer above the second dielectric layer, wherein the third dielectric layer comprises the same dielectric material as the first dielectric material.