6F2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6F2 dram array and a method of isolating a single row of memory cells in a 6F2 dram array
First Claim
1. A 6F2 DRAM array including:
- a first memory cell including a first access transistor and a first data storage capacitor, a first load electrode of the first access transistor being coupled to the first data storage capacitor via a first storage node formed on the substrate;
a second memory cell including a second access transistor and a second data storage capacitor, a first load electrode of the second access transistor being coupled to the second data storage capacitor via a second storage node formed on the substrate, the first and second access transistors each including a gate dielectric with a first thickness; and
an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween, the isolation gate including an isolation gate dielectric with a second thickness that is greater than the first thickness used in at least the access transistors.
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Abstract
The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.
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Citations
29 Claims
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1. A 6F2 DRAM array including:
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a first memory cell including a first access transistor and a first data storage capacitor, a first load electrode of the first access transistor being coupled to the first data storage capacitor via a first storage node formed on the substrate;
a second memory cell including a second access transistor and a second data storage capacitor, a first load electrode of the second access transistor being coupled to the second data storage capacitor via a second storage node formed on the substrate, the first and second access transistors each including a gate dielectric with a first thickness; and
an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween, the isolation gate including an isolation gate dielectric with a second thickness that is greater than the first thickness used in at least the access transistors. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A DRAM array formed on a semiconductive substrate and including:
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a first memory cell including a first access device and a first data storage capacitor, a first load electrode of the first access device being coupled to the first data storage capacitor via a first storage node formed on the substrate;
a second memory cell including a second access device and a second data storage capacitor, a first load electrode of the second access device being coupled to the second data storage capacitor via a second storage node formed on the substrate, the first and second access devices having a first threshold voltage; and
an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween, the isolation gate having a second threshold voltage that is greater than the first threshold voltage. - View Dependent Claims (8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21)
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13. A method of forming memory cells in a 6F2 DRAM array including:
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forming a first memory cell including a first access transistor and a first data storage capacitor, a first load electrode of the first access transistor being coupled to the first data storage capacitor via a first storage node formed on the substrate;
forming a second memory cell including a second access transistor and a second data storage capacitor, a first load electrode of the second access transistor being coupled to the second data storage capacitor via a second storage node formed on the substrate, wherein forming the first and second memory cells includes forming the first and second access transistors to have gate dielectrics with a first thickness; and
forming an isolation gate between the first and second storage nodes and configured to provide electrical isolation therebetween, wherein forming the isolation gate includes forming an isolation gate dielectric to have a second thickness that is greater than the first thickness used in at least the first and second access transistors.
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22. A method of isolating a single row of memory cells in a 6F2 DRAM array comprising:
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providing pairs of rows of memory cells, each row including a plurality of access devices each having a gate dielectric with a first thickness; and
providing an isolation gate separating rows comprising each pair of rows, each isolation gate having a gate dielectric with a second thickness, the second thickness being greater than the first thickness, the isolation gates being configured to isolate one of the pair of rows from another of the pair of rows in response to application of a suitable voltage. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29)
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Specification