Partitioned radio-frequency apparatus and associated methods

• US 20020132648A1
• Filed: 03/29/2001
• Published: 09/19/2002
• Est. Priority Date: 01/12/2001
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Scott, Jeffrey W., Tuttle, G. Tyson, Behrens, Richard T., Vishakhadatta, G. Diwakar, Srinivasan, Vishnu Shankar, Kerth, Donald A.
• Granted Patent: US 6,804,497 B2
• Time in Patent Office: Days
• US Class Current: 455/570
• CPC Class Codes: H04B 1/0003 Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00
• CPC Class Codes: H04B 1/109 by improving strong signal performance of the receiver when strong unwanted signals are present at the receiver input
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04B 1/406 with more than one transmission mode, e.g. analog and digital modes
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder
• CPC Class Codes: H04B 2215/064 Reduction of clock or synthesizer reference frequency harmonics

Abstract

Radio-frequency (RF) apparatus includes receiver analog circuitry that receives an RF signal and provides at least one digital signal to receiver digital circuitry that functions in cooperation with the receiver analog circuitry. The receiver analog circuitry and the receiver digital circuitry are partitioned so that interference effects between the receiver analog circuitry and the receiver digital circuitry tend to be reduced.

Claims

1. A radio-frequency (RF) apparatus, comprising:

a first circuit partition, comprising receiver analog circuitry configured to produce a digital receive signal from an analog radio-frequency signal; and

a second circuit partition, comprising receiver digital circuitry configured to accept the digital receive signal, wherein the first and second circuit partitions are partitioned so that interference effects between the first circuit partition and the second circuit partition tend to be reduced.

2. The RF apparatus of claim 1, in which the first circuit partition comprises transmitter circuitry configured to receive at least one transmit input signal and to provide a transmit RF signal.

3. The RF apparatus of claim 2, in which the transmitter circuitry comprises transmit voltage-controlled oscillator (VCO) circuitry.

4. The RF apparatus of claim 3, in which the first circuit partition resides within a first integrated circuit device and the second circuit partition resides within a second integrated circuit device.

5. The RF apparatus of claim 3, comprising a third circuit partition that includes local-oscillator circuitry configured to provide a radio-frequency (RF) signal to the receiver analog circuitry and to the transmitter circuitry, the local-oscillator circuitry further configured to provide an intermediate-frequency (IF) signal to the transmitter circuitry, wherein the first, second, and third circuit partitions are partitioned so that interference effects among the first, second, and third circuit partitions tend to be reduced.

6. The RF apparatus of claim 5, in which the first circuit partition resides within a first integrated circuit device, the second circuit partition resides within a second integrated circuit device, and the third circuit partition resides within a third integrated circuit device.

7. The RF apparatus of claim 5, in which the receiver digital circuitry comprises digital-to-analog converter (DAC) circuitry configured to produce an analog receive signal.

8. The RF apparatus of claim 7, in which the first circuit partition resides within a first integrated circuit device, the second circuit partition resides within a second integrated circuit device, and the third circuit partition resides within a third integrated circuit device.

9. A radio-frequency (RF) transceiver, comprising:

a first circuit partition, comprising;

receiver analog circuitry configured to accept a received RF signal and to provide at least one digital output signal; and

transmitter circuitry configured to receive at least one transmit input signal and to provide a transmit RF signal;

a second circuit partition, comprising local-oscillator circuitry configured to accept a reference signal, the local oscillator circuitry further configured to provide a radio-frequency (RF) signal to the receiver analog circuitry and to the transmitter circuitry, wherein the first circuit partition and the second circuit partition are partitioned so that interference effects between the first circuit partition and the second circuit partition tend to be reduced.

10. The transceiver of claim 9, in which the transmitter circuitry within the first circuit partition comprises transmit voltage-controlled oscillator (VCO) circuitry.

11. The transceiver of claim 10, in which the receiver analog circuitry provides the at least one digital output signal to baseband processor circuitry external to both the first and second circuit partitions.

12. The transceiver of claim 11, in which the receiver analog circuitry comprises:

analog down-converter circuitry configured to accept the received RF signal, the down-converter circuitry further configured to provide an analog down-converted signal; and

analog-to-digital converter (ADC) circuitry coupled to the baseband processor circuitry, the analog-to-digital converter circuitry configured to receive the analog down-converted signal, the analog-to-digital circuitry further configured to provide the at least one digital output signal of the receiver analog circuitry.

13. The transceiver of claim 12, in which the transmitter circuitry comprises baseband up-converter circuitry configured to accept the at least one transmit input signal, the baseband up-converter circuitry further configured to provide an intermediate frequency (IF) signal to offset phase-lock loop (PLL) circuitry coupled to the transmit voltage-controlled oscillator circuitry.

14. The transceiver of claim 13, comprising reference generator circuitry external to both the first and second circuit partitions, the reference generator circuitry configured to provide the reference signal to the second circuit partition.

15. The transceiver of claim 14, in which the reference generator circuitry resides within the baseband processor circuitry.

16. The transceiver of claim 14, in which the baseband processor circuitry receives the at least one digital output signal of the receiver analog circuitry, and in which the baseband processor circuitry provides the at least one transmit input signal to the baseband up-converter circuitry.

17. The transceiver of claim 16, in which the first circuit partition resides within a first integrated circuit device and the second circuit partition resides within a second integrated circuit device.

18. The transceiver of claim 10, comprising a third circuit partition that includes receiver digital circuitry configured to receive the at least one digital output signal of the receiver analog circuitry, wherein the first, second, and third circuit partitions are partitioned so that interference effects among the first, second, and third circuit partitions tend to be reduced.

19. The transceiver of claim 18, in which in which the receiver analog circuitry comprises:

analog down-converter circuitry configured to accept the received RF signal, the down-converter circuitry further configured to provide an analog down-converted signal; and

analog-to-digital converter (ADC) circuitry configured to receive the analog down-converted signal, the analog-to-digital circuitry further configured to provide the at least one digital output signal of the receiver analog circuitry.

20. The transceiver of claim 19, in which the receiver digital circuitry comprises:

digital down-converter circuitry configured to accept the at least one digital output signal of the receiver analog circuitry, the digital down-converter circuitry further configured to provide at least one digital down-converted signal; and

digital filter circuitry configured to receive the at least one digital down-converted digital signal, the digital filter circuitry further configured to provide at least one digital filtered signal.

21. The transceiver of claim 20, in which the transmitter circuitry comprises baseband up-converter circuitry configured to accept the at least one transmit input signal, the baseband up-converter circuitry further configured to provide an intermediate frequency (IF) signal to offset phase-lock loop (PLL) circuitry coupled to the transmit voltage-controlled oscillator circuitry.

22. The transceiver of claim 21, comprising reference generator circuitry external to the first, second, and third circuit partitions, the reference generator circuitry configured to provide the reference signal to the second and third circuit partitions.

23. The transceiver of claim 22, in which external baseband processor circuitry receives the at least one filtered digital signal of the digital filter circuitry, and in which the baseband processor circuitry provides to the baseband up-converter circuitry the at least one transmit input signal.

24. The transceiver of claim 23, in which the reference generator circuitry resides within the baseband processor circuitry.

25. The transceiver of claim 24, in which the first circuit partition resides within a first integrated circuit device, the second circuit partition resides within a second integrated circuit device, and the third circuit partition resides within a third integrated circuit device.

26. The transceiver of claim 22, in which the receiver digital circuitry comprises digital-to-analog converter (DAC) circuitry configured to accept from the digital filter circuitry the at least one filtered digital signal, the digital-to-analog-converter circuitry configured to provide at least one analog receive signal.

27. The transceiver of claim 26, in which the first circuit partition resides within a first integrated circuit device, the second circuit partition resides within a second integrated circuit device, and the third circuit partition resides within a third integrated circuit device.

29. The method of claim 28, which further comprises:

providing in the first circuit partition a transmitter circuitry; and

utilizing the transmitter circuitry to receive at least one transmit input signal and to provide a transmit RF signal.

30. The method of claim 29, which further comprises including in the transmitter circuitry a voltage-controlled oscillator (VCO) circuitry.

31. The method of claim 30, which further comprises:

integrating the first circuit partition within a first integrated circuit device; and

integrating the second circuit partition within a second integrated circuit device.

32. The method of claim 30, which further comprises:

providing a third circuit partition that includes local-oscillator circuitry;

utilizing the local-oscillator circuitry to provide a radio-frequency (RF) signal to the receiver analog circuitry and to the transmitter circuitry;

further utilizing the local-oscillator circuitry to provide an intermediate-frequency (IF) signal to the transmitter circuitry; and

partitioning the first, second, and third circuit partitions so that interference effects among the first, second, and third circuit partitions tend to be reduced.

33. The method of claim 32, which further comprises:

integrating the first circuit partition within a first integrated circuit device;

integrating the second circuit partition within a second integrated circuit device; and

integrating the third circuit partition within a third integrated circuit device.

34. The method of claim 32, which further comprises:

including digital-to-analog converter (DAC) circuitry within the receiver digital circuitry; and

converting the digital receive signal into an analog receive signal by utilizing the digital-to-analog circuitry.

35. The method of claim 34, which further comprises:

integrating the first circuit partition within a first integrated circuit device;

integrating the second circuit partition within a second integrated circuit device; and

integrating the third circuit partition within a third integrated circuit device.

37. The method of claim 36, which further comprises including within the transmitter circuitry a transmit voltage-controlled oscillator (VCO) circuitry.

38. The method of claim 37, which further includes utilizing the receiver analog circuitry to provide the at least one digital output signal to baseband processor circuitry external to both the first and second circuit partitions.

39. The method of claim 38, which further includes:

including analog down-converter circuitry within the receiver analog circuitry;

utilizing the analog down-converter circuitry to accept the received RF signal and to supply an analog down-converted signal;

providing analog-to-digital converter (ADC) circuitry within the receiver analog circuitry;

coupling the analog-to-digital converter circuitry to the baseband processor circuitry; and

utilizing the analog-to-digital converter circuitry to receive the analog down-converted signal and to supply the at least one digital output signal of the receiver analog circuitry.

40. The method of claim 39, which further includes:

providing offset phase-lock loop (PLL) circuitry;

coupling the offset phase-lock loop circuitry to the transmit voltage-controlled oscillator circuitry;

including within the transmitter circuitry a baseband up-converter circuitry; and

utilizing the baseband up-converter circuitry to accept the at least one transmit input signal and to supply an intermediate frequency (IF) signal to the offset phase-lock loop circuitry.

41. The method of claim 40, which further comprises:

providing reference generator circuitry external to both the first and second circuit partitions; and

utilizing the reference generator circuitry to provide the reference signal to the second circuit partition.

42. The method of claim 41, which further comprises including the reference generator circuitry within the baseband processor circuitry.

43. The method of claim 41, which further includes utilizing the baseband processor circuitry to receive the at least one digital output signal of the receiver analog circuitry and to supply the at least one transmit input signal to the baseband up-converter circuitry.

44. The method of claim 43, which further includes:

integrating the first circuit partition within a first integrated circuit device; and

integrating the second circuit partition within a second integrated circuit device.

45. The method of claim 37, which further comprises:

providing a third circuit partition that includes receiver digital circuitry;

utilizing the receiver digital circuitry to receive the at least one digital output signal of the receiver analog circuitry; and

partitioning the first, second, and third circuit partitions so that interference effects among the first, second, and third circuit partitions tend to be reduced.

46. The method of claim 45, which further comprises:

providing analog down-converter circuitry within the receiver analog circuitry;

utilizing the analog down-converter circuitry to accept the received RF signal and to supply an analog down-converted signal;

providing analog-to-digital converter (ADC) circuitry within the receiver analog circuitry; and

converting the analog down-converted signal into the at least one digital output signal of the receiver analog circuitry by using the analog-to-digital converter circuitry.

47. The method of claim 46, which further comprises:

providing digital down-converter circuitry within the receiver digital circuitry;

utilizing the digital down-converter circuitry to accept the at least one digital output signal of the receiver analog circuitry and to supply at least one digital down-converted signal;

providing digital filter circuitry within the receiver digital circuitry; and

filtering the at least one digital down-converted digital signal by using the digital filter circuitry to produce at least one digital filtered signal.

48. The method of claim 47, which further comprises:

providing offset phase-lock loop (PLL) circuitry;

coupling the offset phase-lock loop circuitry to the transmit voltage-controlled oscillator circuitry;

including baseband up-converter circuitry within the transmitter circuitry; and

utilizing the baseband up-converter circuitry to accept the at least one transmit input signal and to supply an intermediate frequency (IF) signal to the offset phase-lock loop circuitry.

49. The method of claim 48, which further includes:

providing reference generator circuitry external to the first, second, and third circuit partitions; and

utilizing the reference generator circuitry to provide the reference signal to the second and third circuit partitions.

50. The method of claim 49, which further includes:

providing external baseband processor circuitry; and

utilizing the external baseband processor circuitry to receive the at least one filtered digital signal of the digital filter circuitry and to supply to the baseband up-converter circuitry the at least one transmit input signal.

51. The method of claim 50, which further comprises providing the reference generator circuitry within the baseband processor circuitry.

52. The method of claim 51, which further comprises:

integrating the first circuit partition within a first integrated circuit device;

integrating the second circuit partition within a second integrated circuit device; and

integrating the third circuit partition within a third integrated circuit device.

53. The method of claim 49, which further comprises:

providing digital-to-analog converter (DAC) circuitry within the receiver digital circuitry; and

to utilizing the digital-to-analog converter circuitry to accept from the digital filter circuitry the at least one filtered digital signal and to provide at least one analog receive signal.

54. The method of claim 53, which further comprises:

integrating the first circuit partition within a first integrated circuit device;

integrating the second circuit partition within a second integrated circuit device; and

integrating the third circuit partition within a third integrated circuit device.

28. A method of partitioning radio-frequency (RF) apparatus, comprising:

providing a first circuit partition that comprises receiver analog circuitry;

utilizing the receiver analog circuitry to produce a digital receive signal from an analog radio-frequency signal;

providing a second circuit partition comprising receiver digital circuitry;

utilizing the receiver digital circuitry to accept the digital receive signal; and

partitioning the first and second circuit partitions so that interference effects between the first circuit partition and the second circuit partition tend to be reduced.

36. A method of partitioning radio-frequency (RF) transceiver circuitry, comprising:

providing a first circuit partition that includes a receiver analog circuitry and a transmitter circuitry;

utilizing the receiver analog circuitry to accept a received RF signal and to provide at least one digital output signal;

utilizing the transmitter circuitry to receive at least one transmit input signal and to provide a transmit RF signal;

providing a second circuit partition that includes local-oscillator circuitry;

utilizing the local-oscillator circuitry to accept a reference signal, and to provide a radio-frequency (RF) signal to the receiver analog circuitry and to the transmitter circuitry; and

partitioning the first circuit partition and the second circuit partition so that interference effects between the first circuit partition and the second circuit partition tend to be reduced.