Method of driving a display device

• US 20020135313A1
• Filed: 03/21/2002
• Published: 09/26/2002
• Est. Priority Date: 03/22/2001
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun
• Granted Patent: US 6,693,385 B2
• Time in Patent Office: Days
• US Class Current: 315/169.3
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0847 being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
• CPC Class Codes: G09G 2310/0272 Details of drivers for data electrodes, the drivers communicating data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/3241 the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
• CPC Class Codes: G09G 3/3283 in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H10K 50/80 Constructional details
• CPC Class Codes: H10K 50/8423 Metallic sealing arrangements
• CPC Class Codes: H10K 50/8426 Peripheral sealing arrangements, e.g. adhesives, sealants
• CPC Class Codes: H10K 50/844 Encapsulations
• CPC Class Codes: H10K 59/1201 : Manufacture or treatment
• CPC Class Codes: H10K 59/1213 : the pixel elements being TFTs

Abstract

A driving method that does not allow a change in temperature of the surroundings to change the luminance of a light emitting element of a pixel is provided for a display device with less uneven display, higher gradation, and reduced power consumption. A time ratio gradation driving method is applied to a pixel that is structured to have a current mirror circuit and use a current drive method. The bit number of digital video signals to be sampled by a source signal line driving circuit is reduced with the use of a switching signal, thereby saving the power consumption when high gradation display is not necessary.

Claims

1. A method of driving a display device, said method comprising the steps of:

inputting a constant signal current into a pixel;

wherein the pixel emits a light with a constant luminance by the constant signal current;

dividing one frame period into a plurality sub frame periods,

wherein whether the pixel emits the tight or not is determined in each of the plurality of sub frame periods.

7. A method according to claim 1,

the display device is in combination with an electronic apparatus.

8. A method according to claim 7,

wherein the electronic apparatus is one selected from the group consisting of a portable information terminal a personal computer, an image reproducing device, a television, a head mounted display and a video camera.

2. A method of driving a display device, said method comprising the steps of:

inputting a first current into a pixel;

converting the first current into a voltage;

holding the voltage;

converting the voltage into a second current;

inputting the second current into a light emitting element of the pixel;

wherein the light emitting element emits a light with a constant luminance;

dividing one frame period into a plurality of sub frame periods,

wherein whether the pixel emits the light or not is determined in each of the plurality of sub frame periods.

9. A method according to claim 2,

the display device is in combination with an electronic apparatus.

10. A method according to claim 9,

wherein the electronic apparatus is one selected from the group consisting of a portable information terminal, a personal computer, an image reproducing device, a television, a head mounted display and a video camera.

3. A method of driving a display device,

said display device comprising:

a pixel including a first thin film transistor, a second thin film transistor and a light emitting element;

said method comprising the steps of;

inputting a first current into the pixel;

wherein the first current is a first drain current of the first thin film transistor operated in a saturation range;

holding a first gate voltage of the first thin film transistor;

wherein the first gate voltage of the thin film transistor is a second gate voltage of the second thin film transistor;

inputting a second drain current of the second thin film transistor into the light emitting element;

wherein the light emitting element emits a light with a constant luminance;

dividing one frame period into a plurality of sub frame periods,

wherein whether the pixel emits the light or not is determined in each of the plurality of sub frame periods.

11. A method according to claim 3,

the display device is in combination with an electronic apparatus.

12. A method according to claim 11,

wherein the electronic apparatus is one selected from the group consisting of a portable information terminal, a personal computer, an image reproducing device, a television, a head mounted display and a video camera.

14. A method according to claim 13,

wherein the electronic apparatus is one selected from the group consisting of a portable information terminal, a personal computer, an image reproducing device, a television, a head mounted display and a video camera.

17. A method according to claim 15,

wherein the one frame period is divided into a plurality of sub frame periods, and

wherein each of the plurality of sub frame periods includes a display period in which whether or not the light emitting element in each of the plurality of pixels emits a light is determined.

18. A method according to claim 17, further comprising the step of:

inputting n bits digital video signals from an external,

wherein n is a natural number,

wherein the plurality of sub frame period include r sub frame periods,

wherein r is a natural number equal to or larger than n,

wherein n periods are combined with display periods of the r sub frame periods,

wherein a ratio of lengths of the n periods is set to 2⁰;

2<sup>−

1</sup>;

2<sup>−

2</sup>;

. . .2<sup>−

(n−

2)</sup>;

2<sup>−

(n−

1)</sup>.

19. A method according to claim 17, further comprising the step of:

inputting n-bits digital video signals from an external,

wherein n is a natural number,

wherein the plurality of sub frame periods include n sub frame periods; and

wherein a ratio of lengths of respective display periods of the n sub frame periods is set to 2⁰;

2<sup>−

1</sup>;

2²;

. . .2<sup>−

(n−

2)</sup>;

2<sup>−

(n−

1)</sup>.

20. A method according to claim 17,

wherein m bits digital video signals are not sampled by the source signal line driving circuit,

wherein m is a natural number smaller than n.

21. A method according to claim 20,

wherein the m bits digital video signals correspond to lower m bits digital video signals of the n bits digital video signals.

22. A method according to claim 21,

wherein sub frame periods corresponding to the lower m bits digital video signals include no-sampling-pulse periods in which a shift register in the source signal line driving circuit stops outputting sampling pulses.

23. A method according to claim 21,

wherein sub frame periods corresponding to the lower m bits digital video signals include,

reset periods, and

no-sampling-pulse periods in which a shift register in the source signal line driving circuit stops outputting sampling pulses.

24. A method according to claim 23,

wherein the display device includes a reset circuit for changing the digital video signals into an output of a constant electric potential, and

wherein a ‘

0’

signal is inputted from the reset circuit to the source signal line driving circuit during the reset period to be sampled, and

wherein the ‘

0’

signal is outputted to the plurality of source signal lines.

25. A method according to claim 22,

wherein the display device includes a start pulse controlling circuit for changing a start pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.

26. A method according to claim 22,

wherein the display device includes a clock pulse controlling circuit for changing a clock pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.

27. A method according to claim 22,

wherein the display device includes a sampling pulse controlling circuit for changing a sampling pulse to be outputted from the shift register into an output of a constant electric potential during the no-sampling-pulse period.

28. A method according to claim 23,

wherein the display device includes a start pulse controlling circuit for changing a start pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.

29. A method according to claim 23,

wherein the display device includes a clock pulse controlling circuit for changing a clock pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.

30. A method according to claim 23,

wherein the display device includes a sampling pulse controlling circuit for changing a sampling pulse to be outputted from the shift register into an output of a constant electric potential during the no-sampling-pulse period.

31. A method according to claim 24,

wherein the reset circuit comprises at least a NAND and at least an inverter,

wherein the digital video signals and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the reset circuit through the inverter.

32. A method according to claim 25,

wherein the start pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the start pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the start pulse controlling circuit through the inverter.

33. A method according to claim 26,

wherein the clock pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the clock pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the clock pulse controlling circuit through the inverter.

34. A method according to claim 27,

wherein the sampling pulse controlling, circuit comprises at least a NAND and at least an inverter,

wherein the sampling, pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the sampling pulse controlling circuit through the inverter.

35. A method according to claim 28,

wherein the start pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the start pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the start pulse controlling circuit through the inverter.

36. A method according to claim 29,

wherein the clock pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the clock pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the clock pulse controlling circuit through the inverter.

37. A method according to claim 30,

wherein the sampling pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the sampling pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the sampling pulse controlling circuit through the inverter.

38. A method according to claim 15,

wherein the light emitting element comprises an organic material in a light emitting layer.

39. A method according to claim 15,

wherein the light emitting element comprises an inorganic material in a light emitting layer.

40. A method according to claim 15,

wherein the display device is in combination with an electronic apparatus,

wherein the electronic apparatus is one selected from the group consisting of a portable information terminal, a personal computer, an image reproducing device, a television, a head-mounted display and a video camera.

41. A method according to claim 16,

wherein the one frame period is divided into a plurality of sub frame periods, and

wherein each of the plurality of sub frame periods includes a display period in which whether or not the light emitting element in each of the plurality of pixels emits a light is determined.

42. A method according to claim 41, further comprising the step of:

inputting n bits digital video signals from an external,

wherein n is a natural number,

wherein the plurality of sub frame period include r sub frame periods,

wherein r is a natural number equal to or larger than n,

wherein n periods are combined with display periods of the r sub frame periods,

wherein a ratio of lengths of the n periods is set to 2⁰;

2<sup>−

1</sup>;

2²;

. . .;

2<sup>−

(n−

2)</sup>;

2<sup>−

(n−

1)</sup>.

43. A method according to claim 41, further comprising the step of:

inputting n-bits digital video signals from an external,

wherein n is a natural number,

wherein the plurality of sub frame periods include n sub frame periods; and

wherein a ratio of lengths of respective display periods of the n sub frame periods is set to 2⁰;

2<sup>−

1</sup>;

2²;

. . .;

2<sup>−

(n−

2)</sup>;

2<sup>−

(n−

1)</sup>.

44. A method according to claim 41,

wherein m bits digital video signals are not sampled by the source signal line driving circuit,

wherein m is a natural number smaller than n.

45. A method according to claim 44,

wherein the m bits digital video signals correspond to lower m bits digital video signals of the n bits digital video signals.

46. A method according to claim 45,

wherein sub frame periods corresponding to the lower m bits digital video signals include no-sampling-pulse periods in which a shift register in the source signal line driving circuit stops outputting sampling, pulses.

47. A method according to claim 45,

wherein sub frame periods corresponding to the lower m bits digital video signals include,

reset periods, and

no-sampling-pulse periods in which a shift register in the source signal line driving circuit stops outputting sampling pulses.

48. A method according to claim 47,

wherein the display device includes a reset circuit for changing the digital video signals into an output of a constant electric potential, and

wherein a ‘

0’

signal is inputted from the reset circuit to the source signal line driving circuit during the reset period to be sampled, and

wherein the ‘

0’

signal is outputted to the plurality of source signal lines.

49. A method according to claim 46,

wherein the display device includes a start pulse controlling circuit for changing a start pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.

50. A method according to claim 46,

wherein the-display device includes a clock pulse controlling circuit for changing a clock pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.

51. A method according to claim 46,

wherein the display device includes a sampling pulse controlling circuit for changing a sampling pulse to be outputted from the shift register into an output of a constant electric potential during the no-sampling-pulse period.

52. A method according to claim 47,

wherein the display device includes a start pulse controlling circuit for changing a start pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.

53. A method according to claim 47,

wherein the display device includes a clock pulse controlling circuit for changing a clock pulse to be inputted to the shift register into an output of a constant electric potential during the no-sampling-pulse period.

54. A method according to claim 47,

wherein the display device includes a sampling pulse controlling circuit for changing a sampling, pulse to be outputted from the shift register into an output of a constant electric potential during, the no-sampling-pulse period.

55. A method according to claim 48,

wherein the reset circuit comprises at least a NAND and at least an inverter,

wherein the digital video signals and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the reset circuit through the inverter.

56. A method according to claim 49,

wherein the start pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the start pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the start pulse controlling circuit through the inverter.

57. A method according to claim 50,

wherein the clock pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the clock pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the clock pulse controlling circuit through the inverter.

58. A method according to claim 51,

wherein the sampling pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the sampling pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the sampling pulse controlling circuit through the inverter.

59. A method according to claim 52,

wherein the start pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the start pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the start pulse controlling circuit through the inverter.

60. A method according to claim 53,

wherein the clock pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the clock pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the clock pulse controlling circuit through the inverter.

61. A method according to claim 54,

wherein the sampling pulse controlling circuit comprises at least a NAND and at least an inverter,

wherein the sampling pulse and switching signals are inputted to the NAND, and

wherein signals outputted from the NAND are outputted from the sampling pulse controlling circuit through the inverter.

62. A method according to claim 16,

wherein the light emitting element comprises an organic material in a light emitting layer.

63. A method according to claim 16,

wherein the light emitting element comprises an inorganic material in a light emitting layer.

64. A method according to claim 16,

wherein the display device is in combination with an electronic apparatus,

wherein the electronic apparatus is one selected from the group consisting of a portable information terminal, a personal computer, an image reproducing device, a television, a head-mounted display and a video camera.

4. A method of driving a display device,

said display device comprising:

a plurality of pixels;

a driver circuit inputted with n bits digital signals, wherein n is a natural number;

said method comprising the steps of;

inputting a constant signal current into each of the plurality of pixels;

wherein each of the plurality of pixels emits a light with a constant luminance by the constant signal current;

dividing one frame period into a plurality of sub frame periods;

selecting an output of a constant current into each of the plurality of pixels in accordance with each of a first bit digital signal to an n-th bit digital signal among the n bits digital signals by the driver circuit in each of the plurality of sub frame periods,

wherein whether the pixel emits the light or not is determined.

5. A method according to claim 4,

wherein an m-th bit digital signal to the n-th digital signal among the n bits digital signals are not sampled by the driver circuit,

wherein m is a natural number smaller than n.

6. A method according to claim 5,

wherein the m-th bit digital signal to the n-th digital signal correspond to lower m bits digital signals of the n bits digital signals.

13. A method according to claim 4,

the display device is in combination with an electronic apparatus.

15. A method of driving a display device,

said display device comprising:

a source signal tine driving circuit;

a gate signal line driving circuit;

a selection line driving circuit; and

a pixel portion,

said pixel portion comprising;

a plurality of pixels;

a plurality of source signal lines;

a plurality of gate signal lines; and

a plurality of power supply lines,

each of the plurality of pixels including;

a switching thin film transistor;

a current mirror circuit comprising a first thin film transistor and a second thin film transistor; and

a light emitting element,

wherein a gate electrode of the first thin film transistor is connected to a gate electrode of the second thin film transistor,

said method comprising the steps of;

inputting a signal current from the source signal line driving circuit into the plurality of source signal lines;

selecting one of the plurality of gate signal lines by the gate signal line driving circuit;

inputting a current into the light emitting element from one of the plurality of power supply lines through a source region and a drain region of the second thin film transistor in a pixel in which a source region and drain region of the switching thin film transistor is turned conductive;

wherein the light emitting element emits a light,

wherein whether or not the signal current is outputted to the plurality of source signal lines is selected to determine whether the light emitting element emits the light or not,

wherein a luminance is determined by the total length of time the light emitting element emits the light in one frame period.

16. A method of driving a display device,

said display device comprising:

a source signal line driving circuit;

a gate signal line driving circuit;

a selection line driving circuit; and

a pixel portion,

said pixel portion comprising;

a plurality of pixels;

a plurality of source signal lines;

a plurality of gate signal lines;

a plurality of power supply lines; and

a plurality of selection lines,

each of the plurality of pixels including;

a first switching thin film transistor;

a second switching thin film transistor;

a current mirror circuit comprising a first thin film transistor and a second thin film transistor; and

a light emitting element,

wherein one of a source region and drain region of the first switching thin film transistor is connected to one of the plurality of source signal lines,

wherein the other of the source and drain regions of the first switching thin film transistor is connected to one of a source region and a drain region of the second switching thin film transistor and to one of a source region and a drain region of the first thin film transistor,

wherein a gate electrode of the first switching thin film transistor is connected to one of the plurality of gate signal lines,

wherein the other of the source drain regions of the second switching thin film transistor is connected to a gate electrode of the first thin film transistor and a gate electrode of the second thin film transistor,

wherein the other of the source drain regions of the first thin film transistor is connected to one of the plurality of power supply lines,

wherein a gate electrode of the second switching thin film transistor is connected to one of the plurality of selection lines,

wherein one of a source region and a drain region of the second thin film transistor is connected to one of the plurality of power supply lines,

wherein the other of the source region and drain regions of the second thin film transistor is connected to the light emitting element,

said method comprising the steps of;

inputting a signal current into the plurality of source signal lines from the source signal line driving circuit;

selecting one of the plurality of gate signal lines by the gate signal line driving circuit;

selecting one of the plurality of selection lines by the selection line driving circuit;

wherein the signal current flows between the source and drain regions of the first thin film transistor in a pixel in which the source and drain regions of the first switching thin film transistor is turned conductive and the source and drain regions of the second switching thin film transistor is turned conductive;

inputting a current into the light emitting element from one of the plurality of power supply lines through a source region and a drain region of the second thin film transistor,

wherein whether or not the signal current is outputted to the plurality of source signal lines is selected to determine whether the light emitting element emits the light or not,

wherein a luminance is determined by the total length of time the light emitting element emits the light in one frame period.