Memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays

• US 20020136045A1
• Filed: 06/29/2001
• Published: 09/26/2002
• Est. Priority Date: 03/21/2001
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Granted Patent: US 6,567,287 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

The preferred embodiments described herein provide a memory device with row and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. In one preferred embodiment, a memory device is provided with its row decoder circuits and column decoder circuits arranged in a checkerboard pattern under a plurality of memory arrays. Because each of the row decoder and column decoder circuits is associated with the memory array above its location and an adjacent array, a denser support circuit arrangement is provided as compared to prior approaches. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.

Claims

1. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein the row decoder circuits and the column decoder circuits are arranged in a checkerboard pattern under the plurality of memory arrays.

2. The invention of claim 1 further comprising only one set of wordline drivers between adjacent row decoder circuits, whereby wordlines are continuous between memory arrays over adjacent row decoder circuits.

3. The invention of claim 1 further comprising two sets of wordline drivers between adjacent row decoder circuits, whereby wordlines are not continuous between memory arrays over adjacent row decoder circuits.

4. The invention of claim 1 further comprising only one set of bitline drivers between adjacent column decoder circuits, whereby bitlines are continuous between memory arrays over adjacent column decoder circuits.

5. The invention of claim 1 further comprising two sets of bitline drivers between adjacent column decoder circuits, whereby bitlines are not continuous between memory arrays over the adjacent column decoder circuits.

6. The invention of claim 1, wherein wordlines in a memory array are interleaved from two sets of wordline drivers.

7. The invention of claim 1, wherein bitlines in a memory array are interleaved from two sets of bitline drivers.

8. The invention of claim 1 further comprising at least one additional row decoder circuit not under a memory cell.

9. The invention of claim 1 further comprising at least one additional column decoder circuit not under a memory cell.

10. The invention of claim 1, wherein at least one row decoder circuit comprises a plurality of wordline decoders, and wherein the plurality of wordline decoders are connected to a respective plurality of wordlines through a respective plurality of switches.

11. The invention of claim 1, wherein at least one column decoder circuit comprises a plurality of bitline decoders, and wherein the plurality of bitline decoders are connected to a respective plurality of bitlines through a respective plurality of switches.

12. The invention of claim 1, wherein the memory cells of the plurality of memory arrays comprise a semiconductor material.

13. The invention of claim 1, wherein the memory cells of the plurality of memory arrays comprise an organic polymer.

14. The invention of claim 1, wherein the memory cells of the plurality of memory arrays comprise a phase change material.

15. The invention of claim 1, wherein the memory cells of the plurality of memory arrays comprise an amorphous solid.

16. The invention of claim 1, wherein the plurality of memory arrays are fabricated above a substrate.

17. The invention of claim 1, further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays.

18. The invention of claim 1, wherein the plurality of memory arrays comprise write-once memory cells.

19. The invention of claim 1 further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays, wherein wordlines in each memory array are interleaved from two sets of wordline drivers, wherein bitlines in each memory array are interleaved from two sets of bitline drivers, and wherein each memory array comprises a plurality of anti-fuse memory cells.

20. A memory device comprising:

a plurality of memory arrays;

a plurality of row decoder circuits; and

a plurality of column decoder circuits;

wherein at least one of the plurality of row decoder circuits is associated with a memory array above its location and an adjacent memory array, and wherein at least one of the plurality of column decoder circuits is associated with a memory array above its location and an adjacent memory array.

21. The invention of claim 20 further comprising only one set of wordline drivers between adjacent row decoder circuits, whereby wordlines are continuous between memory arrays over adjacent row decoder circuits.

22. The invention of claim 20 further comprising two sets of wordline drivers between adjacent row decoder circuits, whereby wordlines are not continuous between memory arrays over adjacent row decoder circuits.

23. The invention of claim 20 further comprising only one set of bitline drivers between adjacent column decoder circuits, whereby bitlines are continuous between memory arrays over adjacent column decoder circuits.

24. The invention of claim 20 further comprising two sets of bitline drivers between adjacent column decoder circuits, whereby bitlines are not continuous between memory arrays over the adjacent column decoder circuits.

25. The invention of claim 20, wherein wordlines in a memory array are interleaved from two sets of wordline drivers.

26. The invention of claim 20, wherein bitlines in a memory array are interleaved from two sets of bitline drivers.

27. The invention of claim 20 further comprising an additional plurality of memory arrays vertically-stacked above the first-mentioned plurality of memory arrays, wherein wordlines in each memory array are interleaved from two sets of wordline drivers, wherein bitlines in each memory array are interleaved from two sets of bitline drivers, and wherein each memory array comprises a plurality of anti-fuse memory cells.