Time synchronization for data over a powerline modem network

• US 20020141523A1
• Filed: 04/03/2001
• Published: 10/03/2002
• Est. Priority Date: 04/03/2001
• Status: Active Grant

• Current Assignee: Freetek Holdings LLC (IP Edge LLC)
• Original Assignee: Thomson Licensing SA (Vantiva SA)
• Inventors: Ramaswamy, Kumar, Litwin, Louis Robert Jr.
• Granted Patent: US 6,834,091 B2
• Time in Patent Office: Days
• US Class Current: 375/356
• CPC Class Codes: H04B 2203/545 Audio/video application, e.g. interphone
• CPC Class Codes: H04B 2203/5495 having measurements and testing channel
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04J 3/0638 Clock or time synchronisation among nodes; Internode synchronisation synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

Synchronization of a powerline modem network (10) with a plurality of devices is provided. A plurality of devices (16 and 18) each include a powerline modem (20) and a clock circuit (22) for synchronizing a data rate. The powerline modem permits data transmission between the plurality of devices over a powerline network on data carriers (28). A synchronization signal is transmitted over the powerline network. The synchronization signal includes a carrier (30) operating at a frequency different from the data carriers. The synchronization signal provides each of the plurality of devices a time reference to synchronize the data rate.

Claims

1. A method of synchronization of a powerline modem network for a plurality of devices, comprising the steps of:

providing a plurality of devices each having a powerline modem and a clock circuit for synchronizing a data rate, the powerline modem permitting data transmission between the plurality of devices over a powerline network on data carriers; and

transmitting a synchronization signal over the powerline network, the synchronization signal being a carrier operating at a frequency different from the data carriers, the synchronization signal providing each of the plurality of devices a time reference to synchronize the data rate.

2. The method as recited in claim 1, wherein the step of transmitting a synchronization signal includes transmitting the synchronization signal over a plurality of carriers operating at a frequency different from the data carriers.

3. The method as recited in claim 1, wherein the step of transmitting a synchronization signal includes the step of sending a current timestamp to the plurality of devices.

4. The method as recited in claim 3, further comprising the step of each of the plurality of devices sounding off during an assigned time slot.

5. The method as recited in claim 1, further comprising the step of determining an error offset between the assigned time slot and the sounding off of the device.

6. The method as recited in claim 1, further comprising the step of transmitting a correction factor to the plurality of devices to correct synchronization of the clock circuit of the devices, which include error offsets.

7. A powerline network with data synchronization, comprising:

a plurality of devices each having a powerline modem and a clock circuit for synchronizing a data rate, the powerline modem permitting data transmission between the plurality of devices over the powerline network on data carriers; and

a master device having a powerline modem coupled to the powerline network and including a clock transmission circuit, the clock transmission circuit generates a synchronization signal over the powerline network, the synchronization signal being a carrier operating at a frequency different from the data carriers, the synchronization signal providing each of the plurality of devices a time reference to synchronize the data rate.

8. The network as recited in claim 7, wherein the synchronization signal includes a plurality of carriers operating at a frequency different from the data carriers.

9. The network as recited in claim 7, wherein the synchronization signal includes a current timestamp which causes each of the plurality of devices to sound off during an assigned time slot.

10. The network as recited in claim 9, further comprising a correction factor sent to each the plurality of devices by the master device to correct synchronization of the clock circuit of the devices, which include error offsets, the error offset being a difference between the assigned time slot and the sounding off of the device.