MULTIPLE MODE MEMORY MODULE

• US 20020144049A1
• Filed: 09/21/1999
• Published: 10/03/2002
• Est. Priority Date: 05/05/1989
• Status: Active Grant

• Current Assignee: Edward D. Mann
• Original Assignee: Edward D. Mann
• Inventors: MANN, EDWARD D.
• Granted Patent: US 6,523,100 B2
• Time in Patent Office: Days
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

A memory unit 18 includes a bus 16 which couples the memory unit to a memory control unit 14. The memory unit includes a latch for receiving and storing an address from the bus, a first memory plane for storing information units associated with an odd address, a second memory plane for storing information units associated with an even address, an input latch for receiving from the bus an information unit associated with a received address and output latches for storing, prior to transmission to the bus, a stored information unit associated with a received address. The memory unit further includes logic, responsive to a state of a first bus signal line, for enabling the output latches to (a) simultaneously transmit to the bus an information unit from both the first and the second memory planes, or (b) sequentially transmit to the bus an information unit from one of the memory planes followed by an information unit from the other one of the memory planes.

Claims

1. A memory unit for storing information units, the memory unit including means for coupling to a bus having a plurality of signal lines, the memory unit further comprising, in combination, means for receiving an address from the bus, memory storage means for storing information units associated with addresses, means for receiving from the bus an information unit associated with a received address, means for transmitting to the bus an information unit associated with a received address, and means, responsive to a state of a first bus signal line, for enabling said transmitting means to (a) simultaneously transmit a plurality of stored information units to a plurality (x) of bus signal lines, or (b) sequentially transmit at least one stored information unit to a plurality (y) of bus signal lines, and wherein x>

y.

2. A memory unit as set forth in claim 1 wherein the memory storage means is organized as a first memory storage means and as a second memory storage means, the memory unit further comprising:

first address generation means having a plurality of outputs coupled to the first memory storage means;

second address generation means having a plurality of outputs coupled to the second memory storage means; and

wherein each of the first and the second address generation means each comprise counter means coupled to the address receiving means, each of the counter means including means for storing a portion of the received address and means for incrementing the stored address for consecutively accessing a plurality of associated memory storage means storage locations.

3. A memory unit as set forth in claim 2 and further comprising means for incrementing the first and the second counter means, the incrementing means being responsive to a state of a second bus signal line for causing the incrementing means to increment the first and the second counter means, the incrementing means further being responsive to a third bus signal line for enabling, when the third bus signal line is asserted, the incrementing means to increment the first and the second counter means when the second bus signal line is asserted.

4. A memory unit as set forth in claim 2 wherein the first address generation means further includes adder means coupled between the address receiving means and the counter means for selectively incrementing the address prior to the counter means storing means storing the portion of the received address.

5. A memory unit as set forth in claim 1 and further comprising:

match generation means responsive to the received address for generating a match signal on a condition wherein the received address is within a range of addresses associated with the memory unit, the match generating means comprising first driver means having an output coupled to the bus for asserting a bus signal expressive of the matched condition.

6. A memory unit as set forth in claim 5 and further comprising second driver means having an output coupled to the bus for asserting a bus signal expressive of a type of memory device which comprise the first and the second memory storage means.

7. A memory unit as set forth in claim 6 wherein the bus signal expressive of a type of memory device is asserted to indicate that the memory devices are static column dynamic RAMs.

8. A memory unit as set forth in claim 5 and further comprising third driver means having an output coupled to the bus for asserting a bus signal expressive of an access speed of memory devices which comprise the first and the second memory storage means.

9. A memory unit as set forth in claim 8 wherein the bus includes a reference timing clock signal and wherein the bus signal expressive of an operating speed is asserted to indicate that an additional one half of a cycle of the reference timing clock signal is required to access the memory devices.

10. A memory unit for storing data which is interconnected during operation with a memory control unit, the memory unit comprising a bus coupling the memory unit to the memory control unit by a plurality of signal lines, the plurality of signal lines including a first plurality of control and status signal lines and at least one second plurality of signal lines including a multiplexed address/data bus having a width of a double-word of data, the memory unit further comprising, in combination, means for storing an address received from the second plurality of signal lines, first memory storage means for storing double words of data associated with an odd address, second memory storage means for storing double words of data associated with an even address, means for receiving from the second plurality of signal lines at least a word or a double-word of data associated with a received address, means for transmitting to at least the second plurality of signal lines a stored double-word of data associated with a received address, and means, responsive to a state of a first one of the control and status signal lines, for determining if the bus to which the memory unit is coupled includes only the second plurality of signal lines or whether the bus to which the memory unit is coupled also includes a third plurality of signal lines, the third plurality of signal lines including a data bus having a width of a double-word of data.

11. A memory unit as set forth in claim 10 and further comprising means, responsive to the operation of the determining means, for enabling the transmitting means to (a) simultaneously transmit to the second plurality of signal lines a double-word of data from the first memory storage means and to the third plurality of signal lines a double-word of data from the second memory storage means, or (b) sequentially transmit to the second plurality of signal lines a double-word of data from one of the memory storage means followed by a double-word of data from the other one of the memory storage means.

12. A memory unit as set forth in claim 11 and further comprising:

first address generation means having a plurality of outputs coupled to the first memory storage means;

second address generation means having a plurality of outputs coupled to the second memory storage means;

wherein each of the first and the second address generation means each comprise column address generation means comprising counter means coupled to the address storage means, each of the counter means including means for storing a portion of the address representative of a dynamic RAM column address and means for incrementing the stored column address for consecutively accessing a plurality of associated memory storage means storage locations; and

the memory unit further comprising means for incrementing the first and the second counter means, the incrementing means being responsive to a state of a second one of the control and status signal lines for causing the incrementing means to increment the first and the second counter means, the incrementing means further being responsive to a state of a third one of the control and status signal lines for enabling, when the third one of the control and status signal lines is asserted, the incrementing means to increment the first and the second counter means.

13. A memory unit as set forth in claim 12 wherein the second address generation means further includes adder means coupled between the address storage means and the counter means for incrementing the portion of the address prior to the counter means storing means storing the portion of dynamic RAM column address, the second address generation means further including means for activating the adder means only when the address stored within the address storage means indicates that a first memory access is to be made to the first memory storage means.

14. A memory unit as set forth in claim 11 wherein the transmitting means includes a latch means having inputs coupled to an output of the second memory storage means and an output coupled to an output of the first memory storage means.

15. A memory unit as set forth in claim 10 and further comprising address match generation means comprising means responsive to the stored address for generating a match signal on a condition wherein the stored address is within a range of addresses associated with the memory unit, the memory unit further comprising:

first driver means having an output coupled to the bus for asserting on one of the first plurality of signal lines a first status signal expressive of the matched condition;

second driver means having an output coupled to the bus for asserting on one of the first plurality of signal lines a second status signal expressive of a type of dynamic RAM devices which comprise the first and the second memory storage means; and

third driver means having an output coupled to the bus for asserting on one of the first plurality of signal lines a third status signal expressive of an access speed of the dynamic RAM memory devices which comprise the first and the second memory storage means.

16. A memory unit as set forth in claim 15 wherein the bus signal expressive of a type of dynamic RAM memory device is asserted to indicate that the memory devices are static column dynamic RAMs.

18. A method as set forth in claim 17 wherein the step of providing an address includes, within the memory unit, the steps of:

generating a match signal on a condition wherein the provided address is within a range of addresses associated with the memory unit;

asserting on one of the first plurality of signal lines a first status signal expressive of the matched condition;

asserting on one of the first plurality of signal lines a second status signal expressive of a type of dynamic RAM device which comprises the memory means; and

asserting on one of the first plurality of signal lines a third status signal expressive of an access speed of the dynamic RAM devices which comprise the memory means.

19. A method as set forth in claim 18 wherein if the type of dynamic RAM device is a page mode type of dynamic RAM the step of asserting and deasserting additionally causes a dynamic RAM column address strobe signal to be deasserted and reasserted to initiate a next memory device access cycle.

17. In an information processing system having at least one memory unit for storing information units which is interconnected during operation with a memory control unit, the memory unit being coupled to the memory control unit by a bus comprised of a plurality of signal lines, the plurality of signal lines including a first plurality of control and status signal lines and at least one second plurality of signal lines including a multiplexed address and data bus, the memory unit further comprising, in combination, means for storing an address received from the second plurality of signal lines, memory means including a first memory storage means for storing information units associated with an odd address and a second memory storage means for storing information units associated with an even address, means for receiving from the second plurality of signal lines information units associated with a received address, means for transmitting to at least the second plurality of signal lines stored information units associated with a received address, a method of operating the memory control unit to consecutively store or retrieve information units including the steps of:

providing to the memory unit on the second plurality of signal lines an address of a first address location within the memory means from which to store or retrieve an information unit;

storing within the memory unit a portion of the address which corresponds to at least a portion of a column address, the column address portion being stored within a counter means;

asserting one of the first plurality of signal lines to provide a row address strobe signal to the memory unit to initiate a first access to the memory location specified by the provided address; and

for each additional memory access subsequent to the first access,

asserting and deasserting one of the first plurality of signals such that the portion of the column address stored within the counter means is incremented to a next consecutive column address.

20. A memory unit for storing words of data and responding to an address specifying one of the words by outputting a sequence of words beginning at the word specified by the address, the memory unit comprising:

storage means for storing the words and responding to the address by simultaneously outputting a sequence of (a+b) words where the sequence begins at the word specified by the address and (b) is less than or equal to (a);

signal receiving means for receiving a signal that the memory unit is coupled to a first memory bus having a width of (a+b) words; and

data receiving means coupled to the storage means, to the signal receiving means and, in the alternative, to the first memory bus or to a second memory bus having a width of (a) words, for receiving the (a+b) words from the storage means and outputting (a+b) words simultaneously to the first memory bus in response to the signal or outputting the (a) words followed by the (b) words to the second memory bus.