STRUCTURE HAVING REDUCED LATERAL SPACER EROSION

• US 20020146897A1
• Filed: 03/31/2000
• Published: 10/10/2002
• Est. Priority Date: 12/22/1995
• Status: Active Grant

• Current Assignee: DSS Technology Management, Inc. (Document Security Systems, Inc.)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Petti, Christopher J., Nulty, James E.
• Granted Patent: US 6,784,552 B2
• Time in Patent Office: Days
• US Class Current: 438/586
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects

Abstract

A process for minimizing lateral spacer erosion of an insulating layer adjacent to a contact region and an apparatus whereby there is provided a contact opening with a small alignment tolerance relative to a gate electrode or other structure are disclosed. The process includes the steps of forming a conductive layer on said semiconductor body then depositing an insulating layer adjacent to the conductive layer. Next, substantially rectangular insulating spacers are formed adjacent to the gate. An etch stop layer is deposited adjacent said insulating layer followed by an etch to remove the etch stop layer material from the contact region. This etch is conducted under conditions wherein the etch removes the etch stop layer but retains the substantially rectangular lateral spacer profile of the first insulating layer. The apparatus is capable of maintaining high quality contacts between the conductive material in the contact region and the underlying device region, such as a source or drain, or some other layer or structure and is an effective structure for small feature size structures, particularly self-aligned contact structures.

Claims

1. A process for minimizing lateral spacer erosion on a contact region, said process comprising:

encapsulating a conducting layer in an insulating layer on said semiconductor body adjacent said contact region, wherein said insulating layer includes a substantially rectangular spacer portion adjacent said contact region;

depositing an etch stop layer adjacent said insulating layer and adjacent said contact region; and

etching a portion of said etch stop layer adjacent said contact region wherein said etching does not significantly erode said spacer portion of said insulating layer.

2. The process of claim 1, wherein said etching step utilizes a plasma etching system.

3. The process of claim 2, wherein an etching condition for said etching step is a low bombardment/high neutral flux condition.

4. The process of claim 3, wherein said etching condition has a low selectivity for said etch stop layer material relative to said first insulating layer material.

5. The process of claim 4, wherein said selectivity is less than or equal to 1:

1.

6. The process of claim 2, wherein said plasma etching system is a Lam 4400 Series plasma etching system.

7. The process of claim 6, wherein said etch stop layer etch is performed using a recipe of 900 mtorr, 100 sccm He, 85 sccm C₂F₆, and 225 watts power.

8. The process of claim 1, including cleaning said exposed portion of said first insulating layer with a sputter etch after said etching of said etch stop layer wherein said spacer portion of said first insulating layer retains its substantially rectangular profile.

9. The process of claim 8, wherein said sputter etch is a radio-frequency sputter etch.

10. The process of claim 1, including depositing a blanket insulating layer adjacent said etch stop layer, forming a patterning layer on said blanket insulating layer wherein said patterning layer exposes said contact region, and etching a portion of said blanket insulating layer over said contact region with a suitable etchant to expose a portion of said etch stop layer prior to said etching of said etch stop layer.

11. The process of claim 10, wherein the blanket layer is planarized.

13. The process of claim 12, wherein said etching step utilizes a plasma etching system.

14. The process of claim 13, wherein an etching condition for said etching step is a low bombardment/high neutral flux condition.

15. The process of claim 14, wherein said etching condition has a low selectivity for said etch stop layer material relative to said first insulating layer material.

16. The process of claim 15, wherein said selectivity is less than or equal to 1:

1.

17. The process of claim 13, wherein said plasma etching system is a Lam 4400 series plasma etching system.

18. The process of claim 17, wherein said etch stop layer etch is performed using a recipe of 900 mtorr, 100 sccm He, 85 sccm C₂F₆, and 225 watts power.

19. The process of claim 12, including cleaning said exposed portion of said first insulating layer with a sputter etch after said etching of said etch stop layer wherein said spacer portion of said first insulating layer retains its substantially rectangular profile.

20. The process of claim 19, wherein said sputter etch is a radio-frequency sputter etch.

21. The process of claim 12, including depositing a blanket insulating layer adjacent said etch stop layer, forming a patterning layer on said blanket insulating layer wherein said patterning layer exposes said contact region, and etching a portion of said blanket insulating layer over said contact region with a suitable etchant to expose a portion of said etch stop layer prior to said etching of said etch stop layer.

22. The process of claim 21, wherein the blanket layer is planarized.

24. The semiconductor apparatus of claim 23, wherein said insulating layer has a spacer portion adjacent said region wherein said spacer portion has a substantially rectangular profile.

25. The semiconductor apparatus of claim 23, wherein said etch stop layer is silicon nitride.

26. The semiconductor apparatus of claim 23, wherein said etch stop layer is silicon dioxide.

12. A process for minimizing lateral spacer erosion on a contact region, said process comprising:

encapsulating a conducting layer in an insulating layer on said semiconductor body adjacent said contact region, wherein said insulating layer includes a substantially rectangular spacer portion adjacent said contact region;

depositing an etch stop layer adjacent said insulating layer and adjacent said contact region; and

etching a portion of said etch stop layer adjacent said contact region wherein said etching delivers a minimal diagonal erosion rate of said spacer portion relative to the vertical erosion rate of said insulating layer.

23. A semiconductor apparatus comprising:

first and second conducting layers spaced apart by a region with an area defined in the substrate;

an insulating layer adjacent said first and second conductive layers; and

an etch stop layer adjacent said insulating layer and over said first and second conducting layers, and a second width between said insulating layer adjacent said first and second conducting layers, and wherein said region has an aspect ratio of 1.0-2.4 said aspect ratio defined as the height of said apparatus relative to the second width of said region.