Universal serial bus circuit

• US 20020147876A1
• Filed: 03/14/2002
• Published: 10/10/2002
• Est. Priority Date: 04/06/2001
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Nokia Corporation
• Inventors: Croyle, Richard
• Granted Patent: US 6,957,292 B2
• Time in Patent Office: Days
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002
• CPC Class Codes: G06F 13/4295 using an embedded synchronisation

Abstract

The invention relates to universal serial bus (USB) circuits utilised in USB devices and USB hubs. Specifically, the invention relates to circuitry used to detect whether the hub or device is connected to a USB host, i.e. to detect connection status of the device or hub. The present invention provides a USB circuit comprising a microprocessor adapted to receive signalling concerning the connection status of the USB circuit to a USB host circuit, first and second data signal lines adapted to transmit respective first and second data signals to the microprocessor, a USB host power supply signal line adapted to receive USB host power signalling to indicate connection status, and wherein the USB circuit is characterised by comprising connection status signalling means adapted to analyze the USB power supply signal line and change the data signal transmitted down the first and second data lines according to the connection status of USB circuit to the USB host circuit.

Claims

1. A USB circuit comprising

a microprocessor adapted to receive signalling concerning the connection status of the USB circuit to a USB host circuit,

first and second data signal lines adapted to transmit respective first and second data signals to the microprocessor,

a USB host power supply signal line adapted to receive USB host power signalling to indicate connection status, and

wherein the USB circuit is characterised by comprising connection status signalling means adapted to analyse the USB power supply signal line and change the data signal transmitted down the first and second data lines according to the connection status of the USB circuit to the USB host circuit.

2. The USB circuit according to claim 1, wherein the connection status signalling means is configured to simultaneously send a ‘

1’

signal down each of the data lines to the microprocessor when the USB circuit is in a disconnected state.

3. The USB circuit according to claim 2, wherein the connection status signalling means comprises a NOT gate and two OR gates, the NOT gate being arranged to provide input into each of the two OR gates, the remaining OR gate inputs each being arranged to be connected to the host end of one of the data signal lines, and wherein the output of the two OR gates is arranged to be connected to the microprocessor end of the corresponding data line.

4. The USB circuit according to claims 2 or 3, wherein the circuit is further adapted to have a NAND logic gate connected to the data lines to convert the simultaneous ‘

1’

signalling state to a single ‘

0’

signal state.

5. The USB circuit according to any of the preceding claims, wherein a signal filter is provided to reduce signal inconsistencies between signalling from the data signal lines.

6. The USB circuit according to claim 4 and 5, wherein a signal filter is connected to the NAND logic gate input to reduce signal inconsistencies.

7. The USB circuit according to claims 4, 5 or 6, wherein the NAND logic gate/signal filter is/are incorporated into the microprocessor.

8. The USB circuit according to any of the preceding claims, wherein the microprocessor and/or connection status signalling means is contained in a USB Digital ASIC.

9. The USB circuit according to any of the preceding claims, wherein the USB circuit comprises a transceiver and the connection status signalling means is incorporated into the transceiver.

10. The USB circuit according to claim 9, wherein the USB circuit comprises a transceiver and the microprocessor is incorporated into the transceiver.

11. The USB circuit according to any one the preceding claims, wherein the USB circuit is incorporated into a USB device.

12. The USB circuit according to any one of claims 1-11, wherein the USB circuit is incorporated into a USB hub.

13. A USB circuit as hereinbefore described and with reference to FIGS. 2 and 3.