ON-CHIP DEBUG SYSTEM WITH A DATA BAND SELECTOR

• US 20020147939A1
• Filed: 01/22/1999
• Published: 10/10/2002
• Est. Priority Date: 01/22/1999
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG)
• Inventors: CHESTERS, ERIC, WENZEL, ANDREAS, FLECK, ROD G., SHEEDY, GARY
• Granted Patent: US 6,516,428 B2
• Time in Patent Office: Days
• US Class Current: 714/30
• CPC Class Codes: G06F 11/3466 Performance evaluation by tracing or monitoring
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

An improved on chip debug system is disclosed. The on chip debug system includes a data band selector arranged to selectively transmit particular data bands generated by a processor included in an integrated circuit as needed to an emulator. The data band selector is directed by the emulator based upon instructions received from a host computer.

Claims

1. An integrated circuit useful for selectively providing operational test data of selected components included therein, the electrical components being responsive to control signals to generate operating data taking the form of data bands, the data bands being used to evaluate the functionality of the integrated circuit, comprising:

a plurality of I/O lines suitably arranged to couple the electrical components to external circuitry, the external circuitry being arranged to provide control signals capable of directing selected electrical components to generate associated data bands in response to a test program; and

a data band selector connected to the plurality of electrical components arranged for selecting certain ones of the data bands as directed by the control signals based upon instructions included in the test program.

2. An integrated circuit as recited in claim 1, wherein at least one of the electrical components is a processor unit.

3. An integrated circuit as recited in claim 1, wherein the data selector includes:

a plurality of input lines connected to the electrical components;

an output data bus connected to external circuitry arranged to carry data bands generated by selected electrical components;

a plurality of tristate drivers having inputs connected to the input lines and outputs connected to the output data bus; and

a tristate driver selector connected to the tristate drivers arranged to enable selected tristate drivers in response to the control signals.

4. An integrated circuit as recited in claim 1, wherein the integrated circuit is a system on a chip type integrated circuit.

5. An on-chip debug system suitable for functional testing of an integrated circuit, comprising:

a host computer arranged to perform executable instructions;

an emulator connected to the host computer arranged to generate control and logic signals based upon instructions received from the host computer; and

a device under test (DUT) integrated circuit connected to the emulator responsive to the control and logic signals generated by the emulator, the device under test (DUT) integrated circuit including,

a plurality of electrical components wherein certain ones of the electrical components respond to external signals by generating an associated data band indicative of a particular operational characteristic of the electrical component, and

a programmable data band selector connected to the certain electrical components arranged to output selected data bands based upon control signals received from the emulator by way of a data band selector control line.

6. A debug system as recited in claim 5, further includes:

a master target board having a master DUT integrated circuit integrally connected therein, the master target board being connected to the emulator;

a slave target board having a slave DUT integrated circuit integrally connected therein, the slave target board being connected to the emulator;

a comparator connected to the master target board and the slave target board, the comparator being arranged to receive a master calibration signal output by the master DUT integrated circuit during operation and to receive a slave calibration signal output by the slave DUT integrated circuit during operation, the comparator compares the master calibration signal and the slave calibration signal and outputs an associated comparator output voltage indicative of the synchrony of operation of the master and slave DUT integrated circuit.

7. A debug system as recited in claim 5, wherein the DUT integrated circuit is a system on a chip type integrated circuit.

8. A debug system as recited in claim 7, wherein the system on a chip type integrated circuit includes a plurality of systems wherein each of the systems generates an associated set of data bands indicative of selected operational characteristics of the system.

9. A debug system as recited in claim 6, wherein the comparator output voltage causes the host computer is direct the emulator to halt debugging of the master DUT integrated circuit and the slave DUT integrated circuit whenever the comparator output signal indicates the master DUT integrated circuit and the slave DUT integrated circuit are not operating in synchrony.

10. A debug system as recited in claim 9 wherein the host computer is a PC.

11. A debug system as recited in claim 9 wherein the host computer is a workstation.

12. A debug system as recited in claim 9 wherein emulator is an automatic tester, the automatic tester incorporating a central processor, a memory, and an I/O device, the automatic tester being arranged to supply instructions to the DUT integrated circuit and post process data bands received from the data band selector.

13. A method of debugging an integrated circuit using an on-chip debug system, the on-chip debug system includes a host computer arranged to perform executable instructions, an emulator connected to the host computer arranged to generate control and logic signals based upon instructions received from the host computer, and a device under test (DUT) integrated circuit connected to the emulator responsive to the control and logic signals generated by the emulator, the device under test (DUT) integrated circuit includes a plurality of electrical components wherein certain ones of the electrical components respond to external signals by generating an associated data band indicative of a particular operational characteristic of the electrical component, and a programmable data band selector connected to the certain electrical components arranged to output selected data bands based upon control signals received from the emulator by way of a data band selector control line, comprising:

(a) selecting a data band to be traced;

(b) selecting a break point used to view operational characteristics of a particular parameter at a specific location in a control flow of the DUT integrated circuit;

(d) loading a test program in the emulator;

(e) executing the test program;

(e) capturing the selected data band;

(f) capturing result data if the break point has been detected;

(g) post processing the captured data band; and

(h) repeating (a) through (g) until all data bands have been captured.