MEMS relay and mehtod of fabricating the same

• US 20020160583A1
• Filed: 01/28/2002
• Published: 10/31/2002
• Est. Priority Date: 04/26/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Song, Hoon
• Granted Patent: US 6,511,894 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: B81B 2201/01 Switches
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: H01H 59/0009 making use of micromechanics

Abstract

A MEMS relay is provided. The MEMS relay includes a first wafer, a second wafer, and a third wafer that are sequentially stacked. The first wafer includes driving electrodes positioned at the bottom surface of the first wafer, input signal electrodes and output signal electrodes formed adjacent to each other and corresponding to the driving electrodes, via holes formed through the first wafer on the driving electrodes, the input signal electrodes, and the output signal electrodes, and metal pads formed over the via holes. The second wafer includes a body including a sealing unit used to hermetically seal the first and third wafers with the second wafer interposed therebetween, a driving unit which is formed inside and isolated from the body, is an integrated body consisting of a silicon substrate, a passivation layer formed on the silicon substrate, and contact electrodes formed on the passivation layer, and is located lower than the top surface of the body by a predetermined distance, and a connection supporter which extends from two opposing sides of the driving unit to the inner surface of the body. The third wafer includes a hollow in which the driving unit can be rotated.

Claims

1. A MEMS relay which comprise a first wafer, a second wafer, and a third wafer that are sequentially stacked, wherein the first wafer comprises:

driving electrodes positioned at the bottom surface of the first wafer;

input signal electrodes and output signal electrodes formed adjacent to each other and corresponding to the driving electrodes;

via holes formed through the first wafer on the driving electrodes, the input signal electrodes, and the output signal electrodes; and

metal pads formed over the via holes, and

the second wafer comprises;

a body including a sealing unit used to hermetically seal the first and third wafers with the second wafer interposed therebetween;

a driving unit which is formed inside and isolated from the body, is an integrated body consisting of a silicon substrate, a passivation layer formed on the silicon substrate, and contact electrodes formed on the passivation layer, and is located lower than the top surface of the body by a predetermined distance; and

a connection supporter which extends from two opposing sides of the driving unit to the corresponding inner surface of the body; and

the third wafer comprises a hollow in which the driving unit can be rotated.

2. The MEMS relay of claim 1, wherein the connection supporter comprises a torsion spring, which extends from the two opposing sides of the driving unit outwardly, and an anchor which connects the torsion spring to the corresponding inner surface of the body.

3. The MEMS relay of claim 1, wherein an electrode supporter is further formed on the third wafer to support each of the input and output signal electrodes.

4. The MEMS relay of claim 1, wherein the second wafer is formed of silicon, and the first and third wafers are formed of Pyrex glass.

5. The MEMS relay of claim 1, wherein the passivation layer is a SiO₂ layer or a Si₃N₄ layer.

6. The MEMS relay of claim 1, wherein ball grid arrays (BGAs) are further formed on the metal pads.

7. A method of fabricating a MEMS relay comprising:

(a) preparing a silicon wafer as a second wafer and two Pyrex glass wafers as first and third wafers;

(b) forming a mask on the second wafer and anisotropically etching the second wafer using the mask;

(c) forming a passivation layer in the middle of the second wafer and forming contact electrodes on the passivation layer by patterning;

(d) forming electrodes at the bottom of the first wafer by patterning;

(e) bonding the first and second wafers to each other;

(f) planarizing the upper portion of the first wafer by chemical mechanical polishing (CMP), forming via holes through the first wafer, and forming metal pads over the via holes;

(g) planarizing the lower portion of the second wafer by CMP, and patterning and etching the bottom portion of the second wafer;

(h) forming a hollow in the third wafer by etching a predetermined portion of the third wafer; and

(i) bonding the third wafer to the lower portion of the second wafer.

8. The method of claim 7 further comprising forming BGAs on the metal pads after the step (f).

9. The method of claim 7, wherein in the step (i), the third wafer and the second wafer are anodically bonded to each other.