Low dielectric constant shallow trench isolation
First Claim
Patent Images
1. An integrated circuit device, comprising:
- a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench contains cells of gaseous components.
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Accused Products
Abstract
Techniques of shallow trench isolation and devices produced therefrom. The techniques of shallow trench isolation utilize foamed polymers, cured aerogels or air gaps as the insulation medium. Such techniques facilitate lower dielectric constants than the standard silicon dioxide due to the cells of gaseous components inherent in foamed polymers, cured aerogels or air gaps. Lower dielectric constants reduce capacitive coupling concerns and thus permit higher device density in an integrated circuit device.
7 Citations
29 Claims
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1. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench contains cells of gaseous components. - View Dependent Claims (2, 3, 4)
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5. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed polymeric material. - View Dependent Claims (6, 7, 8)
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9. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a cured aerogel. - View Dependent Claims (10, 11, 13, 14, 15, 17, 18)
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12. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with an air gap.
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16. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed polyimide material.
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19. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed Type I polyimide material.
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20. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed Type III polyimide material.
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21. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed polynorbornene material.
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22. An integrated circuit device, comprising:
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a first active region formed in a substrate;
a second active region formed in the substrate; and
a trench formed in the substrate and interposed between the first active region and the second active region;
wherein the trench is filled with a foamed methylsilsesquioxane material. - View Dependent Claims (24, 25, 26)
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23. A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of semiconductor devices, wherein at least two of the plurality of semiconductor devices are isolated by an interposing trench, and wherein the trench contains cells of gaseous components.
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27. A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of semiconductor devices, wherein at least two of the plurality of semiconductor devices are isolated by an interposing trench, and wherein the trench is filled with a foamed polymeric material.
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28. A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of semiconductor devices, wherein at least two of the plurality of semiconductor devices are isolated by an interposing trench, and wherein the trench is filled with a cured aerogel.
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29. A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of semiconductor devices, wherein at least two of the plurality of semiconductor devices are isolated by an interposing trench, and wherein the trench is filled with an air gap.
Specification