Integrated circuit device and method of producing the same

• US 20020163079A1
• Filed: 03/28/2002
• Published: 11/07/2002
• Est. Priority Date: 05/02/2001
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Awano, Yuji
• Granted Patent: US 7,084,507 B2
• Time in Patent Office: Days
• US Class Current: 257/750
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/28581 Deposition of Schottky electrodes
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66454 Static induction transistors [SIT], e.g. permeable base transistors [PBT]
• CPC Class Codes: H01L 29/7783 using III-V semiconductor material
• CPC Class Codes: H01L 29/7784 with delta or planar doped donor layer H01L29/7785 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/762 Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
• CPC Class Codes: Y10S 977/765 with specified cross-sectional profile, e.g. belt-shaped
• CPC Class Codes: Y10S 977/766 Bent wire, i.e. having nonliner longitudinal axis

Abstract

An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms. The latter device is preferably manufactured by a method comprising using a CVD process for the formation of the cylindrical structures, while applying a direct current electric field so as to grow the cylindrical structures in one direction, or applying an alternating current electric field so as to grow the cylindrical structures in two directions. A semiconductor device using a carbon nanotube and a method of forming a pattern using a carbon nanotube as a mask are also disclosed.

Claims

1. An integrated circuit device comprising a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, wherein the via is formed of one or more cylindrical structures made up of carbon atoms.

2. The integrated circuit device of claim 1, wherein the via is formed of a single cylindrical structure made up of carbon atoms.

3. The integrated circuit device of claim 1, wherein the via is formed of a plurality of cylindrical structures made up of carbon atoms.

4. The integrated circuit device of claim 3, wherein the via is formed of a bundle of a plurality of cylindrical structures made up of carbon atoms.

5. The integrated circuit device of claim 1, wherein the cylindrical structure is formed of a single cylindrical body.

6. The integrated circuit device of claim 1, wherein the cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

7. The integrated circuit device of claim 2, wherein the cylindrical structure is formed of a single cylindrical body.

8. The integrated circuit device of claim 2, wherein the cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

9. The integrated circuit device of claim 3, wherein the cylindrical structure is formed of a single cylindrical body.

10. The integrated circuit device of claim 3, wherein the cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

11. The integrated circuit device of claim 3, wherein the via includes, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

12. The integrated circuit device of claim 4, wherein the via includes, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

13. The integrated circuit device of claim 1, wherein the via is surrounded by an insulation layer, the insulation layer being formed of a silicon-based insulation material or a porous material.

14. The integrated circuit device of claim 1, wherein the side of the via is exposed.

15. The integrated circuit device of claim 1, wherein part of the vias have a junction structure of a cylindrical structure of metallic properties and a cylindrical structure of semiconductor-like properties.

16. The integrated circuit device of claim 1, wherein other structures exhibiting metallic properties as a whole are present either in the cylindrical structure or between neighboring cylindrical structures, or are present both in the cylindrical structure or between neighboring cylindrical structures.

17. The integrated circuit device of claim 1, wherein the cylindrical structure is a carbon nanotube.

19. The integrated circuit device of claim 18, wherein the wiring member is formed of a single cylindrical structure made up of carbon atoms.

20. The integrated circuit device of claim 18, wherein the wiring member is formed of a plurality of cylindrical structures made up of carbon atoms.

21. The integrated circuit device of claim 20, wherein the wiring member is formed of a bundle of a plurality of cylindrical structures made up of carbon atoms.

22. The integrated circuit device of claim 18, wherein the cylindrical structure is formed of a single cylindrical body.

23. The integrated circuit device of claim 18, wherein the cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

24. The integrated circuit device of claim 19, wherein the cylindrical structure is formed of a single cylindrical body.

25. The integrated circuit device of claim 19, wherein the cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

26. The integrated circuit device of claim 20, wherein the cylindrical structure is formed of a single cylindrical body.

27. The integrated circuit device of claim 20, wherein the cylindrical structure is formed of a plurality of coaxially arranged cylindrical bodies.

28. The integrated circuit device of claim 20, wherein the wiring member includes, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

29. The integrated circuit device of claim 21, wherein the wiring member includes, in combination, one or more cylindrical structures formed of a single cylindrical body and one or more cylindrical structures formed of a plurality of coaxially arranged cylindrical bodies.

30. The integrated circuit device of claim 18, wherein the wiring member is surrounded by an insulation layer, the insulation layer being formed of a porous material.

31. The integrated circuit device of claim 1, wherein the wiring member is exposed.

32. The integrated circuit device of claim 18, wherein part of the wiring members is exposed, and the remainder is embedded in an insulation material.

33. The integrated circuit device of claim 32, wherein the insulation material is porous.

34. The integrated circuit device of claim 18, wherein part of the wiring members has a junction structure of a cylindrical structure of metallic properties and a cylindrical structure of semiconductor-like properties.

35. The integrated circuit device of claim 18, wherein the cylindrical structure is a carbon nanotube.

37. The method of claim 36, wherein the direction of the applied electric field is changed in sequence to thereby provide a three-dimensionally branched wiring structure formed of the wiring members of the grown cylindrical structures.

38. The method of claim 36, wherein in the course of the growth of the cylindrical structures, the CVD process used is changed from one of a plasma CVD process and a thermal CVD process to the other.

40. The semiconductor device of claim 39, which comprises a cylindrical multilayer structure composed of carbon elements, the structure comprising an inner cylinder member having semiconductor-like characteristics and an outer cylinder member having metallic characteristics, a pair of conductors arranged in opposed relation to each other with the outer cylindrical member in-between and connected to the opposed sides of the inner cylindrical member, respectively, and means for applying a voltage to the outer cylinder member.

41. The semiconductor device of claim 39, wherein said outer cylinder member is a continuous structure not segmented and said inner cylinder member is also a continuous structure not segmented.

42. The semiconductor device of claim 40, wherein said outer cylinder member is a continuous structure not segmented and said inner cylinder member is also a continuous structure not segmented.

43. The semiconductor device of claim 39, wherein said outer cylinder member is a discontinuous structure segmented and said inner cylinder member is a continuous structure not segmented.

44. The semiconductor device of claim 40, wherein said outer cylinder member is a discontinuous structure segmented and said inner cylinder member is a continuous structure not segmented.

45. The semiconductor device of claim 41, wherein said outer cylinder member directly contacts a rectifying electrode.

46. The semiconductor device of claim 42, wherein said outer cylinder member directly contacts a rectifying electrode.

47. The semiconductor device of claim 41, wherein said outer cylinder member is opposed to a rectifying electrode through an insulating material interposed therebetween.

48. The semiconductor device of claim 42, wherein said outer cylinder member is opposed to a rectifying electrode through an insulating material interposed therebetween.

49. The semiconductor device of claim 43, wherein said outer cylinder member is segmented at one portion, and each of the segmented outer cylinders directly contacts a rectifying electrode.

50. The semiconductor device of claim 44, wherein said outer cylinder member is segmented at one portion, and each of said segmented outer cylinders directly contacts a rectifying electrode.

51. The semiconductor device of claim 43, wherein said outer cylinder member is segmented at one portion, and each of said segmented outer cylinders is opposed to a rectifying electrode through an insulating material interposed therebetween.

52. The semiconductor device of claim 44, wherein said outer cylinder member is segmented at one portion, and each of said segmented outer cylinders is opposed to a rectifying electrode through an insulating material interposed therebetween.

53. The semiconductor device of claim 43, wherein said outer cylinder member is segmented at two or more portions, and each of the outermost segments of said outer cylinder member contacts an ohmic electrode, and an intermediate segment or segments of said outer cylinder member contact a rectifying electrode.

54. The semiconductor device of claim 44, wherein said outer cylinder member is segmented at two or more portions, and each of the outermost segments of said outer cylinder member contacts an ohmic electrode, and an intermediate segment or segments of said outer cylinder member contact a rectifying electrode.

55. The semiconductor device of claim 53, wherein said intermediate segment of the outer cylinder member directly contacts said rectifying electrode.

56. The semiconductor device of claim 54, wherein said intermediate segment of the outer cylinder member directly contacts said rectifying electrode.

57. The semiconductor device of claim 53, wherein said intermediate segment of the outer cylinder member is opposed to said rectifying electrode through an insulating material interposed therebetween.

58. The semiconductor device of claim 54, wherein said intermediate segment of the outer cylinder member is opposed to said rectifying electrode through an insulating material interposed therebetween.

59. The semiconductor device of claim 57, wherein a side wall of an insulating material is formed on the side surface of said rectifying electrode which faces the outermost segment of said outer cylinder member.

60. The semiconductor device of claim 58, wherein a side wall of an insulating material is formed on the side surface of said rectifying electrode which faces the outermost segment of said outer cylinder member.

61. The semiconductor device of claim 39, wherein said outer cylinder member directly contacts a rectifying electrode, or is opposed to a ractifying electrode through an insulating material interposed therebetween, and wherein the length of said outer cylinder member is not more than the mean free path of electrons.

62. The semiconductor device of claim 40, wherein said outer cylinder member directly contacts a rectifying electrode, or is opposed to a rectifying electrode through an insulating material interposed therebetween, and wherein the length of said outer cylinder member is not more than the mean free path of electrons.

63. The semiconductor device of claim 39, wherein the longitudinal axis of said multilayer structure is parallel to the surface of a substrate on which said multilayer structure is arranged.

64. The semiconductor device of claim 40, wherein the longitudinal axis of said multilayer structure is parallel to the surface of a substrate on which said multilayer structure is arranged.

65. The semiconductor device of claim 39, wherein the longitudinal axis of said multilayer structure is perpendicular to the surface of a substrate on which said multilayer structure is arranged.

66. The semiconductor device of claim 40, wherein the longitudinal axis of said multilayer structure is perpendicular to the surface of a substrate on which said multilayer structure is arranged.

67. The semiconductor device of claim 39, comprising a plurality of said multilayer structures forming a bundle in which the outer cylinder members contact each other.

68. The semiconductor device of claim 40, comprising a plurality of said multilayer structures forming a bundle in which the outer cylinder members contact each other.

69. The semiconductor device of claim 39, wherein said multilayer structure is formed of a plurality of carbon nanotubes.

70. The semiconductor device of claim 40, wherein said multilayer structure is formed of a plurality of carbon nanotubes.

18. An integrated circuit device comprising a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, wherein at least part of the wiring members are formed of one or more cylindrical structures made up of carbon atoms.

36. A method of producing an integrated circuit device comprising a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, wherein at least part of the wiring members are formed of one or more cylindrical structures made up of carbon atoms, the method comprising using a CVD process for the formation of the cylindrical structures, while applying a direct current electric field so as to grow the cylindrical structures in one direction, or applying an alternating current electric field so as to grow the cylindrical structures in two directions.

39. A semiconductor device, which comprises a cylindrical multilayer structure composed of carbon elements, the structure comprising an inner cylinder member having semiconductor-like characteristics and an outer cylinder member having metallic characteristics, and the electric conductivity of said inner cylinder member of said multilayer structure being controlled by a voltage applied to said outer cylinder member.

71. A field effect transistor comprising a source for supplying carriers, a drain for receiving said carriers, and a gate constituting a current control electrode for controlling the current flowing through a channel making up a current path between said source and said drain, by changing the conductivity of said channel, wherein said gate is formed of a metallic carbon nanotube.

72. The field effect transistor of claim 71, wherein the gate of said carbon nanotube is connected to a gate lead-out portion of a metal material.

73. The field effect transistor of claim 72, wherein said gate lead-out portion is fabricated by lithography.

74. The field effect transistor of claim 72, wherein the gate of said carbon nanotube is connected to the gate lead-out portion of said metal material through a catalyst metal for the growth of said carbon nanotube by CVD.

75. The field effect transistor of claim 74, wherein said catalytic metal is a transition metal or an alloy thereof.

76. The field effect transistor of claim 75, wherein said transition metal is selected from Ni, Co and Fe.

77. The field effect transistor of claim 71, wherein said gate of the carbon nanotube is located within a groove formed in a substrate, the groove transversing the channel formed in the substrate.

78. The field effect transistor of claim 77, wherein said groove has a rectangular section.

79. The field effect transistor of claim 77, wherein said groove has a V-shaped section.

80. The field effect transistor of claim 79, wherein said groove accommodating said carbon nanotube is filled with a metal material.

81. A method of fabricating a field effect transistor comprising a source for supplying carriers, a drain for receiving said carriers and a gate constituting a current control electrode for controlling the current flowing through a channel making up a current path between said source and said drain, by changing the conductivity of said channel, said gate being formed of a metallic carbon nanotube,

wherein the gate of the carbon nanotube is grown by a CVD method in the presence of an electric field applied.

82. The method of claim 81, wherein the gate of the carbon nanotube is grown using a catalyst attached to a part of the gate lead-out portion of a metal material to be connected to the gate of the carbon nanotube.

83. The method of claim 82, wherein the gate of the carbon nanotube is grown in one direction from said gate lead-out portion by applying a DC electric field.

84. The method of claim 82, wherein, in addition to the catalyst attached to a part of said gate lead-out portion, a catalyst is arranged at a position where the end of said carbon nanotube which is located far from the portion connected with said gate lead-out portion of said carbon nanotube, and an AC electric field is applied thereby connecting the carbon nanotubes by growing them toward each other from said two positions of the catalysts as origins.

85. The method of claim 81, wherein the gate of said carbon nanotube is grown within a groove formed in a substrate, the groove transversing the channel formed in the substrate.

86. The method of claim 85, wherein said groove has a rectangular section.

87. The method of claim 85, wherein said groove has a V-shaped section.

88. A method of forming a micro pattern, comprising:

arranging a carbon nanotube on a substrate; and

transferring the shape of said carbon nanotube to said substrate by dry etching using said carbon nanotube as a mask, thereby patterning said substrate.

89. The method of claim 88, wherein said substrate is a metal layer.

90. The method of claim 89, wherein said metal layer is for forming the gate of a transistor.

91. The method of claim 89, wherein said substrate is an insulating layer.