Method and apparatus for verifying design data

• US 20020166100A1
• Filed: 05/01/2001
• Published: 11/07/2002
• Est. Priority Date: 05/01/2001
• Status: Active Grant

• Current Assignee: ChipData, Inc.
• Original Assignee: ChipData, Inc.
• Inventors: Meding, Uwe
• Granted Patent: US 6,516,452 B2
• Time in Patent Office: Days
• US Class Current: 716/5
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

Disclosed is an apparatus for comparing CAD (computer aided design) design data comprising one or more components with a set of design rules generated relative said components and generating an output report of detected discrepancies. The output may include data (annotations) used to generate a visually high-lighted (red-lined) display whereby the CAD generated design errors may be easily ascertained. The apparatus includes the capability of transmitting the CAD data, converted to a standardized XML format, from a remote CAD design site to a difference engine site having the latest set of rules relative said components. The difference engine site may then return the results to the remote CAD design site for use by the device design operator. The results returned may be visually displayed in red-lined format as well as in an itemized list.

Claims

1. A method of verifying the correctness of external circuit connections to an electronic chip, comprising the steps of:

generating a set of component circuit design data relative electronic components in a specific circuit configuration;

compiling a set of rules for said electronic components;

comparing the circuit design data for said electronic components with respect to said rules; and

generating a discrepancy report.

2. The method of claim 1, wherein:

the components are electronic chips;

the circuit design data relates to electronic chip pins and the required connections and non-connections to said pins; and

a visually high-lighted display of discrepancies is generated.

3. A method of verifying the correctness of external circuit connections to an electronic chip, comprising the steps of:

interconnecting a verification computer, including a set of pin connection rules for at least one of a plurality of electronic chips, with a second computer having a CAD (computer aided design) program generated circuit design detailing an electronic circuit including said a least one electronic chip;

comparing the pin connection data for each pin with respect to said rules; and

generating a discrepancy report.

4. The method of claim 3, comprising the additional step of generating data for use in creating a high-lighted visual display of circuit design discrepancies.

5. The method of claim 3, comprising the additional step of generating a high-lighted visual display of circuit design discrepancies relative said rules.

6. The method of claim 3, comprising the additional steps of:

making the interconnection over a network;

converting the CAD generated data into an XML format for transmission over the network from said second computer to said verification computer;

assembling the received XML formatted design in a database;

supplying both a red-lined schematic and an item list of discrepancies; and

returning the report to said second computer over the network.

7. The method of claim 3, comprising the additional steps of:

converting the CAD generated data, of said second computer, into an XML format before examination by said verification computer;

assembling the received XML formatted design in a database;

supplying a report comprising both a red-lined schematic and an item list of discrepancies; and

returning the report to said second computer.

8. A method of expediting the detection of circuit design deficiencies of an electronic chip customer by a remote party, comprising the steps of:

sending circuit design data in a standardized format from a customer to the remote party;

examining said circuit design by checking the connections or lack thereof to each pin of an electronic chip incorporated in the circuit design against a set of rules generated by the supplier of said chip; and

returning circuit design discrepancy data from said remote party to said customer.

9. The method of claim 8, wherein:

the remote party is the supplier of said electronic chip; and

the discrepancy data includes visually high-lighted data for display in conjunction with a visualizer at the customer'"'"'s premises.

10. The method of claim 8, comprising the additional steps of:

sorting electronic chip supplier generated rules into primary and secondary rules;

checking the received circuit design data against the primary rules; and

returning a discrepancy data report to said customer, without checking secondary rule discrepancies, when any primary rule discrepancies are detected.

11. The method of claim 8, comprising the additional steps of:

sorting electronic chip supplier generated rules into primary and secondary rules;

checking the received circuit design data against the primary rules;

checking the received circuit design data against the secondary rules; and

returning a discrepancy data report, including a highlighted visual discrepancy presentation, to said customer when rule discrepancies are detected.

13. Apparatus as claimed in claim 12, wherein said components include electronic chips whereby the stored rules include pin connection rules for given electronic chips.

14. Apparatus as claimed in claim 12, comprising, in addition:

sorting means for separating said rules into primary and secondary rules; and

means for reducing difference engine comparison time by eliminating secondary rule comparisons when primary rule discrepancies are detected.

15. Apparatus as claimed in claim 12, comprising, in addition:

means for receiving said stored design data from said CAD circuit design over a network from a remote source; and

means for returning said discrepancy data over said network to said remote source for at least one of visual and written presentation to a circuit designer at said remote source.

17. The method of claim 16, wherein the discrepancy data is used to generate a visual presentation of detected discrepancies.

18. The method of claim 16, comprising the additional steps of:

receiving said data derived from said CAD circuit design over a network from a remote source; and

returning said discrepancy data to said remote source for at least one of high-lighted visual and item list presentation to a circuit designer at said remote source.

20. Apparatus as claimed in claim 19 where said means for presenting the discrepancy data includes display means for visually displaying said circuit design discrepancy data in high-lighted format.

12. Apparatus for detecting electronic component circuit design rule violations in CAD (computer aided design) circuit designs, comprising:

means for storing rules relating to circuit design for given electronic components;

means for storing design data relative a given circuit including said given electronic components; and

difference engine means for comparing said design data and said rules and generating discrepancy data when violations of said rules are detected.

16. A method of ascertaining electronic chip pin connection rule violations in CAD (computer aided design) circuit designs, comprising the steps of:

comparing data derived from said CAD circuit design and pin connection rules applicable to an electronic chip incorporated in said CAD circuit design; and

generating discrepancy data when violations of said rules are detected.

19. Apparatus for expediting the detection of circuit design deficiencies of an electronic chip user by a remote party, comprising:

CAD (computer aided design) circuit means, at a chip user site, for generating circuit design data;

means for sending said circuit design data in a standardized format from said chip user site, over a network, to a remote party site for detecting design deficiencies;

computer means for receiving and examining said circuit design data, at said remote site, by checking the detailed connection design data relative each pin of an electronic chip incorporated in the circuit design against a computer accessible set of rules generated by a manufacturer of said chip;

means for returning circuit design discrepancy data from said remote party site, over said network, to said chip user site; and

means, at said chip user site, for presenting the discrepancy data to an operator of said CAD circuit means in a user friendly format.

21. A method of verifying the correctness of component design usage, comprising the steps of:

generating a set of computer readable design data relative components in a specific design configuration;

compiling a set of rules for usage of said design components;

comparing the circuit design data for said design components with respect to said rules; and

generating a discrepancy report.

22. Apparatus for detecting component design rule violations in CAD (computer aided design) designed apparatus, comprising:

means for storing rules relating to components included in an apparatus design for given design components;

means for storing design data relative a given CAD design including said given design components; and

difference engine means for comparing said design data and said rules and generating discrepancy data when violations of said rules are detected.