Method for identifying an integrated circuit

• US 20020168815A1
• Filed: 04/22/2002
• Published: 11/14/2002
• Est. Priority Date: 10/22/1999
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Hartmann, Ralf
• Granted Patent: US 7,117,414 B2
• Time in Patent Office: Days
• US Class Current: 438/201
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 2029/0407 on power on
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/08 Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An identifier is provided for an integrated circuit with a memory composed of a multiplicity of memory cells. The circuit has a manufacture-related memory cell defect pattern formed of defective memory cells. The method of identifying the integrated circuit utilizes the memory cell defect pattern to generate a circuit identification number for identifying the integrated circuit.

Claims

1. A method of identifying an integrated circuit having a memory formed with a multiplicity of memory cells and having a manufacture-related memory cell defect pattern with defective memory cells, the method which comprises generating a circuit identification number for identifying the integrated circuit from the memory cell defect pattern.

2. The method according to claim 1, which comprises acquiring the addresses of the defective memory cells and generating the circuit identification number based on the addresses of the defective memory cells.

3. The method according to claim 1, which comprises forming the circuit identification number from one or more addresses of the defective memory cells.

4. The method according to claim 1, which comprises generating the circuit identification number by linking a plurality of addresses of the defective memory cells in a calculation operation to generate the circuit identification number.

5. The method according to claim 1, which comprises subsequently reading out the circuit identification number for linking to an equipment program to form an executable equipment program.

6. The method according to claim 5, which comprises storing the linked executable equipment program in a program memory area in order to operate a piece of equipment.

7. The method according to claim 1, which comprises diverting the address of any defective memory cell in each case to an address of a backup memory cell in a redundant memory area of the memory.

8. The method according to claim 1, wherein, for each address of a defective memory cell, in each case an address of an associated backup memory cell is stored in an address conversion memory as an address table.

9. The method according to claim 1, which comprises acquiring the addresses of the defective memory cells once after manufacture of the integrated circuit in a manufacturer test and permanently storing the addresses of the defective memory cells with the addresses of the associated backup memory cells in an address conversion memory for address diversion.

10. The method according to claim 1, which comprises acquiring the addresses of the defective memory cells in a self test whenever the integrated circuit is switched on and storing the addresses of the defective memory cells with the addresses of the associated backup memory cells in an address conversion memory for address diversion.

11. The method according to claim 10, which comprises generating the circuit identification number in dependence on the addresses, acquired in the self test, of the defective memory cells and comparing the circuit identification number with an original circuit identification number by an equipment program, wherein the equipment program enables the associated piece of equipment if the circuit identification number generated in accordance with the self test corresponds to the original circuit identification number.