Multiport-ram memory device

• US 20020184447A1
• Filed: 06/14/2002
• Published: 12/05/2002
• Est. Priority Date: 12/17/1999
• Status: Active Grant

• Current Assignee: Nokia Solutions and Networks GmbH & Co. KG (Nokia Corporation)
• Original Assignee: Siemens AG
• Inventors: Moeller, Heinrich
• Granted Patent: US 6,842,436 B2
• Time in Patent Office: Days
• US Class Current: 711/131
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/4018 with data-width conversion
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention relates to a multiport-RAM memory device, comprising a RAM memory unit (1), a number of serial/parallel converters (5, 6, 7) and a parallel/serial converter (10), for converting serial signals into parallel signals. Said multiport-RAM memory device further comprises a control unit (11) and two timeslot allocation devices (8, 9), whereby an emulation of a number of connections by using the simple RAM memory unit (1) may be achieved. Furthermore, a power controller (12) can significantly reduce the power demand.

Claims

1. A multiport RAM memory device comprising:

a RAM memory unit (1) having an address/control port (2), a read port (3) and a write port (4) for a first time division multiplex system (UR);

an address serial/parallel converter (5) for converting a multiplicity of serial address signals (Adr0 . . . Adr3) of a second time division multiplex system (R) into a multiplicity of parallel address signals of the first time division multiplex system (UR);

a selection serial/parallel converter (6) for converting a multiplicity of serial selection signals (Sel0 . . . Sel3) of the second time division multiplex system (R) into a multiplicity of parallel selection signals of the first time division multiplex system (UR);

a data input serial/parallel converter (7) for converting at least one serial data input signal (DIN0) of the second time division multiplex system (R) into at least one parallel data input signal of the first time division multiplex system (UR);

a first time slot assignment unit (8) for selectively feeding the parallel address signals, lying in predetermined time slots (P0 . . . P4) of the first time division multiplex system (UR), to the address/control port (2) of the RAM memory unit (1);

a second time slot assignment unit (9) for assigning parallel data output signals, read out at the read port (3) of the RAM memory unit (1), into predetermined time slots (P0 . . . P4) of the first time division multiplex system;

a parallel/serial converter (10) for converting the multiplicity of parallel data output signals of the first time division multiplex system (UR) into a multiplicity of serial data output signals (DOUT0 . . . DOUT3) of the second time division multiplex system (R); and

a control unit (11) for controlling the first and second time slot assignment units (8, 9) in a manner dependent on the multiplicity of parallel selection signals.

2. The multiport RAM memory device as claimed in patent claim 1,

characterized by a power control unit (12) for controlling a power consumption of the RAM memory unit (1) in a manner dependent on the control unit (11).

3. The multiport RAM memory device as claimed in patent claim 2,

characterized in that the power control unit (12) controls the power consumption by switching on/off a clock signal (CLK) for the RAM memory unit (1) for a respective time slot (P1) in the first time division multiplex system (UR).

4. The multiport RAM memory device as claimed in one of patent claims 1 to 3,

characterized in that the serial/parallel converters (5, 6, 7) and the parallel/serial converter (10) are synchronized by a synchronizing pulse (SI).

5. The multiport RAM memory device as claimed in one of patent claims 1 to 4,

characterized in that the control unit (11) constitutes a finite state machine.

6. The multiport RAM memory device as claimed in one of patent claims 1 to 5,

characterized in that the control unit (11) drives the second time slot assignment unit (9) in such a way as to compensate for a temporal delay (τ

) during read-out of the parallel data output signals from the RAM memory unit (1).

7. The multiport RAM memory device as claimed in one of patent claims 1 to 6,

characterized in that it constitutes a speech memory (SM0 . . . SM31) in a time switching unit (ZKE) of a switching network in a digital telecommunications switching system.

8. The multiport RAM memory device as claimed in one of patent claims 1 to 7,

characterized in that the multiplicity of serial address signals (Adr0 . . . Adr3) and the multiplicity of serial selection signals (Sel0 . . . Sel3) constitute a multiplicity of control word signals (SW) of a multiplicity of connecting memories (CM0 . . . CM3) in a switching network.

9. The multiport RAM memory device as claimed in one of patent claims 1 to 8,

characterized in that the first time division multiplex system (UR) has n data channels (P0 . . . P4) for the realization of n ports.

10. The multiport RAM memory device as claimed in patent claim 9,

characterized in that the second time division multiplex system (R) has m data channels, a data input signal (DIN0) being assigned to a predetermined write data channel (W) of the n data channels (P0 . . . P4).

11. The multiport RAM memory device as claimed in patent claim 10,

characterized in that further n−

1 n data channels (P0 . . . P4) are assigned to the n−

1 read data channels (R0, R1, R2, R3) or to the n−

1 address signals (Adr0 . . . Adr3) and to the n−

1 data output channels (D0 . . . D3) or to n−

1 data output signals (DOUT0 . . . DOUT3).

12. The multiport RAM memory device as claimed in one of patent claims 9 to 11,

characterized in that n=5 and m=2304.