Power semiconductor devices having linear transfer characteristics and methods of forming and operating same

• US 20020185679A1
• Filed: 07/19/2002
• Published: 12/12/2002
• Est. Priority Date: 06/23/2000
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Silicon Semiconductor Corporation
• Inventors: Baliga, Bantval Jayant
• Granted Patent: US 6,784,486 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7832 the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Power MOSFET devices provide highly linear transfer characteristics (e.g., I_d v. V_g) and can be used effectively in linear power amplifiers. These linear transfer characteristics are provided by a device having a channel that operates in a linear mode and a drift region that simultaneously supports large voltages and operates in a current saturation mode. A relatively highly doped transition region is provided between the channel region and the drift region. Upon depletion, this transition region provides a potential barrier that supports simultaneous linear and current saturation modes of operation. Highly doped shielding regions may also be provided that contribute to depletion of the transition region.

Claims

1. An integrated power device, comprising:

an insulated-gate field effect transistor having an inversion-layer channel therein that operates in a linear mode of operation during forward on-state conduction while a drain region of the transistor simultaneously operates in a velocity saturation mode of operation.

2. The device of claim 1, wherein said transistor comprises:

a semiconductor substrate having a source region and drain contact region of first conductivity type therein;

a base region of second conductivity type extending adjacent a surface of said semiconductor substrate;

a transition region of first conductivity type that extends to the surface and forms a rectifying junction with said base region;

an insulated gate electrode extending on the surface and opposite said source, base and transition regions so that application of a gate bias of sufficient magnitude thereto induces formation of the inversion-layer channel between said source region and said transition region; and

a drift region of first conductivity type that extends between said transition region and said drain contact region, forms a first non-rectifying junction with said transition region and has a first conductivity type doping concentration therein on the drift region side of the first non-rectifying junction that is less than a first conductivity type doping concentration on the transition region side of the first non-rectifying junction.

3. The device of claim 2, further comprising:

means, adjacent said transition region, for fully depleting said transition region while the inversion-layer channel is operating in the linear mode.

4. The transistor of claim 3, wherein said means for fully depleting said transition region comprises a buried region of second conductivity type disposed adjacent said transition region.

5. The transistor of claim 4, wherein said buried region forms a non-rectifying junction with said base region.

6. The transistor of claim 3, wherein said means for fully depleting said transition region comprises a region of second conductivity type that is contiguous with said base region.

7. The transistor of claim 3, further comprising:

a trench that extends in said semiconductor substrate and has a sidewall that defines an interface with said transition region; and

an insulated source electrode that extends in said trench and is electrically connected to said source region.

8. The transistor of claim 7, wherein the device is a vertical device;

wherein the transistor is a lateral transistor;

wherein said semiconductor substrate has first and second opposing faces;

wherein said insulated gate electrode and said source region are formed adjacent the first face; and

wherein said drain contact region is formed adjacent the second face.

9. The transistor of claim 8, wherein the surface and the first face are coextensive.

10. The transistor of claim 9, wherein said drift region extends along the sidewall of said trench.

11. The device of claim 3, wherein said means for fully depleting said transition region comprises:

a first control region of second conductivity type that forms a rectifying junction with said transition region and forms a non-rectifying junction with said base region; and

a second control region of second conductivity type that extends in said transition region and forms a rectifying junction therewith.

12. The device of claim 11, further comprising a source contact that extends on said source region and is electrically connected to said second control region.

13. The device of claim 12, wherein said source contact extends on said base region;

and wherein said first control region is electrically coupled to said source contact by said base region.

14. The device of claim 5, further comprising a source contact that extends on said source region;

and wherein said source contact extends opposite said transition region and forms a MIS junction therewith.

16. The UMOSFET of claim 15, wherein said drift region has a graded doping profile therein that increases in a direction extending from the non-rectifying junction to the drain contact region.

17. The UMOSFET of claim 15, further comprising a buried source electrode in said trench, extending between said insulated gate electrode and a bottom of said trench and electrically connected to said source region.

18. The UMOSFET of claim 15, further comprising means, adjacent said transition region, for fully depleting said transition region while the inversion layer channel is operating in a linear mode of operation.

19. The UMOSFET of claim 18, wherein said means for fully depleting said transition region comprises a base region extension;

and wherein said transition region extends between said base region extension and the sidewall of said trench.

15. A UMOSFET, comprising:

a semiconductor substrate having a source region and a drain contact region of first conductivity type therein;

a trench in said substrate;

an insulated gate electrode in said trench;

a base region of second conductivity type in said semiconductor substrate, said base region extending to a sidewall of said trench so that application of a gate bias of sufficient magnitude to said insulated gate electrode induces formation of an inversion-layer channel in said base region;

a drift region of first conductivity type on the drain contact region, said drift region extending to the sidewall of said trench; and

a transition region that extends between said drift region and said base region and forms non-rectifying and rectifying junctions therewith, respectively, said transition region having a higher first conductivity type doping concentration therein relative to a first conductivity type doping concentration in a portion of said drift region extending adjacent the non-rectifying junction.

20. A MOSFET, comprising:

a semiconductor substrate of first conductivity type having a base region of second conductivity type therein;

a source region of first conductivity type in said base region and forming a P-N junction therewith;

a drain region of first conductivity type in said semiconductor substrate, said drain region comprising a transition region of first conductivity type that extends into said base region and forms a P-N junction therewith;

an insulated gate electrode that extends opposite said base region so that application of a gate bias of sufficient magnitude thereto induces formation of an inversion-layer channel in said base region that extends from said-source-region to said transition region and forms respective non-rectifying junctions with said source region and said transition region during a forward on-state mode of operation; and

means, electrically connected to said base region, for fully depleting said transition region during the on-state mode of operation and before the inversion-layer channel becomes pinched off.

21. The MOSFET of claim 20, wherein said drain region further comprises:

a drift region of first conductivity type that forms a non-rectifying junction with said transition region; and

a drain contact region of first conductivity type that forms a non-rectifying junction with said drift region.

22. The MOSFET of claim 21, wherein said drain contact region is more highly doped than said drift region;

and wherein a maximum first conductivity type doping concentration in said transition region is greater than about ten times a minimum first conductivity type doping concentration in said drift region.

23. The device of claim 20, wherein said means for fully depleting said transition region comprises:

a first control region of second conductivity type that forms a rectifying junction with said transition region and forms a non-rectifying junction with said base region; and

a second control region of second conductivity type that extends in said transition region and forms a rectifying junction therewith.

24. The device of claim 23, further comprising a source contact that extends on said source region and is electrically connected to said second control region.

25. The device of claim 24, wherein said source contact extends on said base region;

and wherein said first control region is electrically coupled to said source contact by said base region.

26. The device of claim 23, further comprising a source contact that extends on said source region;

and wherein said source contact extends opposite said transition region and forms a MIS junction therewith.

28. The device of claim 27, wherein said lateral MOSFET comprises means, adjacent said transition region, for fully depleting said transition region while the inversion-layer channel is operating in the linear mode.

29. The device of claim 28, wherein said means for fully depleting said transition region comprises a buried region of second conductivity type that is electrically connected to a base region of the lateral MOSFET in which the inversion-layer channel is formed during forward on-state conduction.

30. The device of claim 28, wherein said means for fully depleting said transition region comprises a region of second conductivity type that is contiguous with a base region of the lateral MOSFET in which the inversion-layer channel is formed during forward on-state conduction.

27. An integrated power device, comprising:

a lateral MOSFET having an inversion-layer channel therein that operates in a linear mode of operation during forward on-state conduction while a first portion of a drain region of the transistor simultaneously operates in a velocity saturation mode of operation, said drain region comprising a transition region that forms a non-rectifying junction with the inversion-layer channel during forward on-state conduction and is more highly doped than the first portion of the drain region.

31. A lateral MOSFET, comprising:

a semiconductor substrate having a first region of first conductivity type therein extending to a face thereof;

a base region of second conductivity type in the first region and forming a P-N junction therewith;

a source region of first conductivity type in said base region;

a drain contact region of first conductivity type in the first region;

an insulated gate electrode that extends on the face and opposite said base region;

a transition region of first conductivity type that extends in said semiconductor substrate and forms a P-N junction with said base region so that application of a gate bias of sufficient magnitude to said insulated gate electrode induces formation of an inversion-layer channel in said base region that extends from said source region to said transition region; and

a drift region of first conductivity type that extends between said transition region and said drain contact region and forms first and second non-rectifying junctions therewith, respectively, said drift region having a minimum doping concentration therein that is less than a maximum doping concentration in said transition region.

32. The MOSFET of claim 31, further comprising means, adjacent said transition region, for fully depleting said transition region before the inversion-layer channel in said base region becomes pinched-off during a forward on-state mode of operation.

33. The MOSFET of claim 32, wherein said transition region is more lightly doped than said source region and is at least ten times more highly doped than the minimum doping concentration in said drift region.

34. The MOSFET of claim 32, wherein said means for fully depleting said transition region comprises a buried layer of second conductivity type that extends diametrically opposite at least a portion of said transition region, forms a non-rectifying junction with said base region and has a higher second conductivity type doping concentration therein relative to said base region.

35. The MOSFET of claim 34, wherein said buried layer is self-aligned to said transition region.

36. The MOSFET of claim 35, wherein the first region comprises an N-type epitaxial layer.

37. The device of claim 32, wherein said means for fully depleting said transition region comprises:

a first control region of second conductivity type that forms a rectifying junction with said transition region and forms a non-rectifying junction with said base region; and

a second control region of second conductivity type that extends in said transition region and forms a rectifying junction therewith.

38. The device of claim 37, further comprising a source contact that extends on said source region and is electrically connected to said second control region.

39. The device of claim 38, wherein said source contact extends on said base region;

and wherein said first control region is electrically coupled to said source contact by said base region.

40. The device of claim 37, further comprising a source contact that extends on said source region;

and wherein said source contact extends opposite said transition region and forms a MIS junction therewith.

41. A method of operating an insulated-gate field effect transistor, comprising the steps of:

applying a positive voltage to a gate electrode of the transistor; and

fully depleting a portion a drain region of the transistor at the channel/drain junction during on-state conduction while simultaneously applying to the drain region a positive voltage having a magnitude less than a magnitude of the positive voltage applied to the gate electrode.

42. A method of operating an insulated-gate field effect transistor, comprising the steps of:

applying a positive voltage to a gate electrode of the transistor; and

fully depleting a portion a drain region of the transistor at the channel/drain junction during on-state conduction while simultaneously applying to the drain region a positive voltage that induces a positive voltage at the channel/drain junction having a magnitude less than a magnitude of the positive voltage applied to the gate electrode.

43. A method of forming a MOSFET, comprising the steps of:

forming a semiconductor substrate having a source region and drain contact region of first conductivity type therein;

forming a base region of second conductivity type extending adjacent a surface of said semiconductor substrate;

forming a transition region of first conductivity type that extends to the surface and forms a rectifying junction with said base region;

forming an insulated gate electrode extending on the surface and opposite said source, base and transition regions so that application of a gate bias of sufficient magnitude thereto induces formation of the inversion-layer channel; and

forming a drift region of first conductivity type that extends between said transition region and said drain contact region, forms a first non-rectifying junction with said transition region and has a first conductivity type doping concentration therein on the drift region side of the first non-rectifying junction that is less than a first conductivity type doping concentration on the transition region side of the first non-rectifying junction.

44. A method of forming a vertical power device having a lateral MOSFET therein, comprising the steps of:

forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a face of the substrate and has a maximum doping concentration therein that is greater than a minimum doping concentration in the drift region;

forming a base region of second conductivity type that extends through the transition region and into the drift region;

forming a trench that extends through the transition region and into the drift region and has a sidewall that is spaced from the base region by a portion of the transition region;

forming an insulated electrode in the trench;

forming a gate electrode on the face of the semiconductor substrate;

implanting dopants of first conductivity type into the semiconductor substrate to define a source region in the base region and a channel region extension that extends from the base region into the transition region; and

forming a source contact that electrically connects the source region to the insulated electrode in the trench.

45. The method of claim 44, wherein the drift region has a graded doping profile therein;

and wherein the transition region is doped at a level greater than about ten times the minimum doping concentration in the drift region.

46. The method of claim 45, wherein the drift region has a graded doping profile therein;

and wherein the transition region is doped at a level greater than about ten times the minimum doping concentration in the drift region.

48. The device of claim 47, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

49. The device of claim 47, wherein said first and second insulated electrodes are electrically connected to said first and second source regions.

50. The device of claim 47, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

51. The device of claim 47, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

52. The device of claim 47, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of the non-rectifying junction is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

53. The device of claim 47, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region, a width of said transition region at the first depth and a width of the mesa is less than 2×

10¹⁵ cm<sup>−

1</sup>.

54. The device of claim 47, wherein said first source region and said first base region are self-aligned to said insulated gate electrode.

55. The device of claim 47, further comprising:

a first shielding region of second conductivity type that extends between said first base region and the drift region and is more highly doped than said first base region; and

a second shielding region of second conductivity type that extends between said second base region and the drift region and is more highly doped than said second base region.

56. The device of claim 55, wherein said first and second shielding regions form respective P-N rectifying junctions with said transition region;

wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width between said first and second shielding regions is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

57. The device of claim 47, wherein the drift region has a vertically retrograded first conductivity type doping profile therein relative to the surface.

58. The device of claim 47, wherein said insulated gate electrode extends opposite said first and second source regions, said first and second base regions and said transition region.

59. The device of claim 50, wherein the peak first conductivity type dopant concentration in said transition region is greater than about 1×

10¹⁷ cm<sup>−

3</sup>;

wherein the surface defines an interface between said insulated gate electrode and said transition region; and

wherein a first conductivity type dopant concentration in said transition region is less than about 2×

10¹⁶ cm<sup>−

3</sup> at the surface.

60. The device of claim 49, wherein said first insulated electrode ohmically contacts said first base region and said first source region at the sidewall of the first trench.

61. The device of claim 55, wherein the non-rectifying junction extends between said first and second shielding regions.

62. The device of claim 47, further comprising a third trench in said semiconductor substrate, said second and third trenches defining a dummy mesa therebetween into which the drift region extends.

63. The device of claim 62, further comprising a third base region of second conductivity type that extends in the dummy mesa and is electrically connected to said first and second source regions.

64. The device of claim 63, wherein a width of the dummy mesa extending between said second and third trenches equals a width of the mesa extending between said first and second trenches.

65. The device of claim 62, further comprising:

a third insulated electrode in said third trench;

a field plate insulating layer on the dummy mesa; and

a source electrode that extends on said field plate insulating layer and is electrically connected to said first, second and third insulated electrodes.

66. The device of claim 65, wherein a spacing between said first and second trenches is unequal to the spacing between said second and third trenches.

68. The device of claim 67, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

69. The device of claim 67, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

70. The device of claim 67, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

71. The device of claim 67, further comprising:

a first shielding region of second conductivity type that extends between said first base region and the drift region and is more highly doped than said first base region; and

a second shielding region of second conductivity type that extends between said second base region and the drift region and is more highly doped than said second base region.

72. The device of claim 71, wherein said first and second shielding regions form respective P-N rectifying junctions with said transition region;

wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width between said first and second shielding regions is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

73. The device of claim 72, wherein the peak first conductivity type dopant concentration in said transition region is greater than about 1×

10¹⁷ cm<sup>−

3</sup>;

wherein the surface defines an interface between said insulated gate electrode and said transition region; and

wherein a first conductivity type dopant concentration in said transition region is less than about 2×

10¹⁶ cm<sup>−

3</sup> at the surface.

47. A vertical power device, comprising:

a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;

first and second insulated electrodes in the first and second trenches;

first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;

first and second source regions of first conductivity type in said first and second base regions, respectively;

an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region; and

a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to the surface.

67. A vertical power device, comprising:

a semiconductor substrate;

a drift region of first conductivity type in said semiconductor substrate;

first and second spaced-apart base regions of second conductivity type in said semiconductor substrate;

first and second source regions of first conductivity type in said first and second base regions, respectively;

a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to a surface of said semiconductor substrate; and

an insulated gate electrode that extends on the surface and opposite said first base region and said transition region.

74. A vertical power device, comprising:

a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;

first and second insulated electrodes in the first and second trenches, respectively;

a first base region of second conductivity type that extends opposite a sidewall of the first trench and in the mesa;

a first shielding region of second conductivity type that extends opposite the sidewall of the first trench, is more highly doped than said first base region, is disposed between said first base region and the drift region and forms a P-N rectifying junction with the drift region;

a source region of first conductivity type in said first base region;

an insulated gate electrode that extends on the mesa and opposite said first base region; and

a source electrode that extends on said source region and is electrically connected to said first and second insulated electrodes.

75. The vertical power device of claim 74, further comprising:

a transition region of first conductivity type that extends between said first base region and a sidewall of the second trench, forms a P-N rectifying junction and a non-rectifying junction with said first base region and the drift region, respectively, and has a vertically retrograded first conductivity type doping profile relative to a surface of the mesa on which said insulated gate electrode extends.

76. The vertical power device of claim 74, further comprising:

a transition region of first conductivity type that extends between said first base region and a sidewall of the second trench, forms a P-N rectifying junction and a non-rectifying junction with said first base region and the drift region, respectively;

wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to a surface of said substrate; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

77. A vertical power device, comprising:

a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;

first and second insulated electrodes in the first and second trenches;

first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;

first and second source regions of first conductivity type in said first and second base regions, respectively;

an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region; and

a transition region of first conductivity type that extends between said first and second base regions and forms a non-rectifying junction with the drift region, said transition region having a peak first conductivity type dopant concentration therein at a first depth relative to a surface of said substrate; and

wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

78. The vertical power device of claim 77, wherein a product of a width of the mesa and a quantity of first conductivity type charge in a portion of the mesa extending below the transition region is preferably in a range between 2×

10⁹ cm<sup>−

1</sup> and 2×

10¹⁰ cm<sup>−

1</sup>.

79. The vertical power device of claim 77, further comprising third and fourth trenches in said semiconductor substrate, said second and third trenches defining a first dummy mesa therebetween into which the drift region extends and said third and fourth trenches defining a second dummy mesa therebetween into which the drift region extends.

80. A vertical power device, comprising:

a semiconductor substrate having first and second trenches and a drift region of first conductivity type therein that extends into a mesa defined by the first and second trenches;

first and second insulated electrodes in the first and second trenches;

first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;

first and second source regions of first conductivity type in said first and second base regions, respectively;

a first insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region;

a second insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said second base region;

a conductive region that extends between said first and second insulated gate electrodes and opposite the mesa; and

a source electrode that is electrically connected to said first and second source regions and to said conductive region.

81. The device of claim 80, further comprising a transition region of first conductivity type that extends between said first and second base regions, forms a non-rectifying junction with the drift region and has a vertically retrograded first conductivity type doping profile relative to the surface;

and wherein said source electrode extends between opposing sidewalls of the first and second insulated gate electrodes.

82. The device of claim 81, wherein a peak first conductivity type dopant concentration in said transition region is at least ten times greater than a value of the retrograded first conductivity type doping profile at the surface.

83. The device of claim 82, wherein said conductive region comprises a dummy gate electrode.

84. The device of claim 81, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

85. The device of claim 81, wherein said transition region has a peak first conductivity type dopant concentration therein at a first depth relative to the surface;

and wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>.

86. A method of forming a vertical power device, comprising the steps of:

implanting transition region dopants of first conductivity type at a first dose level and first energy level into a surface of a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent the surface;

forming a gate electrode that extends opposite the implanted transition region dopants, on the surface;

implanting shielding region dopants of second conductivity type at a second dose level and second energy level into the surface, using the gate electrode as an implant mask;

implanting base region dopants of second conductivity type at a third dose level and third energy level into the surface, using the gate electrode as an implant mask;

driving the implanted transition, shielding and base region dopants into the substrate to define a transition region that extends in the drift region and has a vertically retrograded first conductivity type doping profile therein relative to the surface, first and second shielding regions that extend on opposite sides of the transition region and form respective P-N rectifying junctions therewith and first and second base regions that extend on opposite sides of the transition region and form respective P-N rectifying junctions therewith; and

implanting source region dopants of first conductivity type into the first and second base regions, using the gate electrode as an implant mask.

87. The method of claim 86, wherein the first dose and energy levels and a duration of said driving step are of sufficient magnitude that a product of a peak first conductivity type dopant concentration in the transition region and a width of the transition region, as measured between the first and second shielding regions, is in a range between 1×

10¹² cm<sup>−

2</sup> and 7×

10¹² cm<sup>−

2</sup>.

88. The method of claim 86, wherein said step of implanting shielding region dopants is preceded by the steps of:

forming trenches in the semiconductor substrate;

lining the trenches with trench insulating layers; and

then

forming conductive regions on the trench insulating layers.

89. The method of claim 88, wherein said step of implanting transition region dopants comprises implanting transition region dopants into the conductive regions within the trenches and into mesas defined between the trenches.

90. The method of claim 88, further comprising the steps of:

etching back the trench insulating layers to expose the source, base and shielding regions; and

forming a source contact that ohmically contacts the conductive, source, base and shielding regions.

91. The method of claim 86, wherein the first and second energy levels are at respective levels that cause a depth of a peak second conductivity type dopant concentration in the shielding region to be within 10% of a depth of a peak first conductivity type dopant concentration in the transition region, when the depths of the peaks are measured relative to the surface.

92. The method of claim 86, wherein the gate electrode is an insulated gate electrode;

wherein the transition region extends to an interface between the insulated gate electrode and the surface; and

wherein a peak first conductivity type dopant concentration in the transition region is greater than about ten times a surface dopant concentration in the transition region.

93. The method of claim 87, wherein said step of implanting shielding region dopants is preceded by the steps of:

forming trenches in the semiconductor substrate;

lining the trenches with trench insulating layers; and

then

forming conductive regions on the trench insulating layers.

94. The method of claim 93, further comprising the steps of:

etching back the trench insulating layers to expose the source, base and shielding regions; and

forming a source contact that ohmically contacts the conductive, source, base and shielding regions.

95. The method of claim 93, wherein the first and second energy levels are at respective levels that cause a depth of a peak second conductivity type dopant concentration in the shielding region to be within 10% of a depth of the peak first conductivity type dopant concentration in the transition region, when the depths of the peaks are measured relative to the surface.

96. The method of claim 87, wherein the gate electrode is an insulated gate electrode;

wherein the transition region extends to an interface between the insulated gate electrode and the surface; and

wherein the peak first conductivity type dopant concentration in the transition region is greater than about ten times a surface dopant concentration in the transition region.

97. A method of forming a vertical power device, comprising the steps of:

forming a trench in a semiconductor substrate having a drift region of first conductivity type therein that extends adjacent a sidewall of the trench;

lining the trench with a trench insulating layer;

forming a trench-based electrode on the trench insulating layer;

forming an insulated gate electrode on a surface of the substrate;

forming a base region of second conductivity type that extends in the substrate and to the sidewall of the trench;

forming a source region of first conductivity type that extends in the base region and to the sidewall of the trench;

etching back the trench insulating layer to expose portions of the base and source regions that extend along the sidewall of the trench; and

forming a source contact that is electrically connected to the base and source regions along the sidewall of the trench.

98. An integrated power device having active and dummy cells therein, comprising:

a semiconductor substrate a drift region of first conductivity type therein;

first, second, third and fourth trenches spaced-apart trenches in said semiconductor substrate, said first and second trenches defining an active mesa therebetween into which the drift region extends, said second and third trenches defining a first dummy mesa therebetween into which the drift region extends and said third and fourth trenches defining a second dummy mesa therebetween into which the drift region extends;

first, second, third and fourth insulated electrodes in said first, second, third and fourth trenches, respectively;

first and second base regions of second conductivity type that extend adjacent sidewalls of the first and second trenches, respectively, and in the mesa;

first and second source regions of first conductivity type in said first and second base regions, respectively;

an insulated gate electrode that extends on a surface of said semiconductor substrate and opposite said first base region; and

a transition region of first conductivity type that extends between said first and second base regions and forms a non-rectifying junction with the drift region, said transition region having a peak first conductivity type dopant concentration therein at a first depth relative to a surface of said substrate; and

wherein the first and second dummy mesas are devoid of a forward on-state current path.

99. The device of claim 98, wherein a product of the peak first conductivity type dopant concentration in said transition region and a width of said transition region at the first depth is in a range between 3.5×

10¹² cm<sup>−

2</sup> and 6.5×

10¹² cm<sup>−

2</sup>; and

wherein a product of a width of the mesa and a quantity of first conductivity type charge in a portion of the mesa extending below the transition region is preferably in a range between 2×

10⁹ cm<sup>−

1</sup> and 2×

10¹⁰ cm<sup>−

1</sup>.