Epitaxial growth method

• US 20020185697A1
• Filed: 06/09/2001
• Published: 12/12/2002
• Est. Priority Date: 06/09/2001
• Status: Active Grant

• Current Assignee: Innovative Foundry Technologies LLC
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Kim, Hyeon-Seag
• Granted Patent: US 6,762,463 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/2807 the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

In accordance with the invention, a MOSFET includes a well, a channel formed in the well, a high K layer overlying the channel, a buffer layer overlying the high k layer, a gate overlaying the buffer layer, a blocking layer overlying the gate and two source/drain regions. In some embodiments the gate and the source/drain regions are silicon germanium.

Claims

1. A device comprising:

a well;

a channel of first conductivity type formed in the well;

a high k layer overlying the channel;

a buffer layer overlying the high k layer;

a gate overlying the buffer layer;

a blocking layer overlying the gate; and

two source/drain regions of second conductivity type formed on opposite sides of the channel.

2. The device of claim 1 wherein each of the high k layer, the buffer layer, and the blocking layer comprise epitaxial layers.

3. The device of claim 1 wherein the gate comprises silicon germanium.

4. The device of claim 1 wherein each of the buffer layer and the blocking layer comprise silicon.

5. The device of claim 1 wherein each of the source/drain regions comprises silicon germanium.

6. The device of claim 5 wherein each of the source/drain regions comprises amorphous silicon germanium.

7. The device of claim 1 wherein the high k layer is selected from the group consisting of oxides of zircon, oxides of titanium, oxides of tantalum, and oxides of hafnium.

8. The device of claim 1 wherein the blocking layer comprises less than or equal to ten layers of atomic silicon.

9. The device of claim 1 wherein the buffer layer comprises less than or equal to ten layers of atomic silicon.

10. A device comprising:

a well;

a channel of first conductivity type formed in the well;

a high k layer overlying the channel;

a gate overlying the high k layer; and

two source/drain regions of second conductivity type formed on opposite sides of the channel, wherein the source/drain regions comprise silicon germanium.

11. The device of claim 10 wherein the gate comprises a metal.

12. The device of claim 10 wherein each of the source/drain regions has a depth of about 100 to about 1000 angstroms.

13. The device of claim 10 wherein the source/drain regions comprise amorphous material.

15. The method of claim 14 wherein growing a high k layer comprises epitaxially growing a metal oxide layer.

16. The method of claim 14 wherein forming two source/drain regions comprises growing amorphous silicon germanium.

17. The method of claim 14 wherein growing a buffer layer comprises growing epitaxial silicon.

18. The method of claim 14 wherein growing a gate comprises growing silicon germanium.

19. The method of claim 14 wherein growing a blocking layer comprises growing epitaxial silicon.

14. A method of forming a device, the method comprising:

forming a well in a substrate;

doping a channel in the well with dopants of a first conductivity type;

growing a high k layer over the channel;

growing a buffer layer over the high k layer;

growing a gate over the buffer layer;

growing a blocking layer over the gate;

removing a portion of the high k layer, the buffer layer, the gate, the blocking layer;

removing a first portion of the well on a first side of the channel and a second portion of the well on a second side of the channel; and

forming two source/drain regions on either side of the channel.