Clock synchronous semiconductor memory device

  • US 20020191480A1
  • Filed: 05/09/2002
  • Published: 12/19/2002
  • Est. Priority Date: 06/13/2001
  • Status: Active Grant
First Claim
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1. A semiconductor device comprising:

  • a plurality of input buffers of different types from each other; and

    program circuitry for generating a signal alternatively driving said plurality of input buffers to an operable state, said plurality of input buffers selectively set to an operable state according to an output signal of said program circuitry and driving an internal node according to a received signal when made active.

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