Semiconductor device and manufacturing method thereof

• US 20030001201A1
• Filed: 01/09/2002
• Published: 01/02/2003
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tsuji, Naoki, Yuzuriha, Kojiro
• Granted Patent: US 6,682,985 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/31053 involving a dielectric removal step
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/76235 trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS

Abstract

A semiconductor device as well as a method of manufacturing a semiconductor device wherein a wide trench separation band is formed without causing the scooping out of the silicon substrate can be gained.

The process is provided with the step of forming a multilayer film on a silicon substrate, the step of patterning the multilayer film and of etching the silicon substrate so as to create a trench, the step of forming an inner wall silicon oxide film on the inner wall surface of the trench, the step of forming a trench oxide layer so as to fill in the trench, the step of polishing the trench oxide layer through CMP polishing so as to expose the silicon nitride layer and the step of etching the trench oxide film, which has undergone the CMP polishing, by a thickness no more than the thickness of the inner wall silicon oxide film.

Claims

1. A method of manufacturing a semiconductor device comprising the steps of:

forming a multilayer film, which includes a silicon oxide layer, a polycrystalline silicon layer located in a layer above the silicon oxide layer and a silicon nitride layer located in a layer above the polycrystalline silicon layer, on a main surface of a silicon substrate;

patterning said multilayer film and, furthermore, of etching a trench for element separation in said silicon substrate;

forming an inner wall silicon oxide film which covers inner wails of said trench by oxidizing the inner wall surfaces which include sidewalls of said multilayer film;

forming a trench oxide layer so as to fill in the trench which is covered with said inner wall silicon oxide film and so as to contact a top surface of said silicon nitride layer;

polishing said trench oxide layer and said silicon nitride layer through CMP polishing so that the thickness of said silicon nitride layer becomes a predetermined thickness and the silicon nitride layer is exposed; and

etching a trench oxide film, which has been formed by polishing said trench oxide layer through said CMP polishing, by a thickness no greater than the thickness of said inner wall silicon oxide film for the purpose of height adjustment of a trench separation band.

2. The method of manufacturing a semiconductor device according to claim 1, wherein the sum of the thickness of the silicon nitride layer after said CMP polishing and the thickness of said polycrystalline silicon layer is larger than the thickness of said inner wall silicon oxide film by no smaller than the amount gained by subtracting the amount of change of the height due to the maximum dispersion of said etching for the purpose of height adjustment of the trench separation from a predetermined separation height.

3. The method of manufacturing a semiconductor device according to claim 1, wherein said silicon nitride layer is formed so as to include the amount of thickness which is to be removed through said CMP polishing.

4. The method of manufacturing a semiconductor device according to claim 1, wherein said trench oxide layer is formed so that the etching rate of said trench oxide film in said etching for height adjustment is greater than the etching rate of said inner wall silicon oxide film.

5. The method of manufacturing a semiconductor device according to claim 1, an oxide layer is formed by means of an HDP (high density plasma) method in the formation of said trench oxide layer.

6. The method of manufacturing a semiconductor device according to claim 1, wherein fluoric acid is used for said etching that is carried out for the purpose of height adjustment of the trench separation band.

7. The method of manufacturing a semiconductor device according to claim 1, wherein said trench is, in a large separation band region of the silicon substrate which includes at least one active region in the plan view, created by etching a separation region between active region external periphery walls, which are formed along the peripheries of respective active regions included in said large separation band region, and inner periphery walls of the large separation band region, which are formed along the periphery of said large separation band region, and said inner wall silicon oxide film is formed on said active region external periphery walls and on said inner periphery walls of the large separation band region so that said trench oxide layer is formed so as to fill in said trench.

8. The method of manufacturing a semiconductor device according to claim 1, wherein said trench is created in said silicon substrate in a band form which includes interconnection films which contact a top surface of the interlayer insulating film on the silicon substrate in the plan view.

9. The method of manufacturing a semiconductor device according to claim 8, wherein said wires are first and second wires arranged in parallel and said trench is created as a region in a band form which includes said first and second wires in the plan view.

10. A semiconductor device manufactured in accordance with the method of claim 1, wherein

said trench separation band comprises a first trench separation band portion and a second trench separation band portion which is wider than said first trench separation band portion.

11. A semiconductor device manufactured in accordance with the method of claim 7, wherein

said trench separation band comprises a first trench separation band portion and a second trench separation band portion which is wider than said first trench separation band portion.

12. A semiconductor device manufactured in accordance with the method of claim 8, wherein

said trench separation band comprises a first trench separation band portion and a second trench separation band portion which is wider than said first trench separation band portion.

13. A semiconductor device manufactured in accordance with the method of claim 9, wherein

said trench separation band comprises a first trench separation band portion and a second trench separation band portion which is wider than said first trench separation band portion.

15. The semiconductor device according to claim 14, wherein the width of said second trench separation band is 6 μ

m even in the narrowest place.

16. The semiconductor device according to claim 14, wherein the region of said second trench separation band includes active regions in which semiconductor elements are provided, wherein the external periphery walls surrounding the active regions are covered with said inner wall silicon oxide film and wherein the width of the second trench separation band is formed of the width of the silicon oxide film which fills in the second trench.

17. The semiconductor device according to claim 14, further comprising an interlayer insulating film on said silicon substrate and wires contact on the top surface of the interlayer insulating film, wherein said second trench separation band is arranged so as to include said wires with band sides running along said wires in the plan view.

18. The semiconductor device according to claim 17, wherein said wires are formed of a plurality of wires running in parallel and said second trench separation band is arranged so as to include said plurality of wires with band sides running along said plurality of wires in the plan view.

14. A semiconductor device comprising a first trench separation band and a second trench separation band which is wider than said first trench separation band, wherein

the position of the top surface of said first trench separation band is located in a position 0 nm to 100 nm higher than the main surface of the silicon substrate,

the position of the top surface of said second trench separation band is in a position lower than the main surface of the silicon substrate and the thickness of the inner wall silicon oxide film which covers the inner walls of the trench in said second trench separation band in the periphery portions of the opening of said second trench is thinner than the thickness of the bottom portion of said trench, and

said second trench separation band has a width such that a recess in a dish form occurs at the time of the CMP polishing of the silicon oxide film which fills in the second trench.