Power MOS element and method for producing the same

• US 20030001215A1
• Filed: 08/21/2002
• Published: 01/02/2003
• Est. Priority Date: 10/02/2001
• Status: Active Grant

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forsching E.V.
• Inventors: Wahl, Uwe, Vogt, Holger
• Granted Patent: US 6,693,011 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A power MOS element includes a drift region with a doping of a first doping type, a channel region with a doping of a second doping type which is complementary to said first doping type and which borders on said channel region and said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region. Furthermore, said power MOS element includes a plurality of basically parallel gate trenches which extend to said drift region and which comprise an electrically conductive material which is insulated from the transistor region by an insulator. The individual gate trenches are connected by a connecting gate trench, a gate contact only being connected in an electrically conductive way to the active gate trenches via contact holes in said connecting gate trench. For producing, three photolithographic steps are sufficient, which serve to etch said gate trenches and said connecting gate trench, to produce said contact holes for said source region and said channel region as well as for said connecting gate trench, and to finally structure said gate contacts and said source contact. Thus, a flexible layout concept is possible in which said gate contact can also be placed in the middle of or at another location on said power MOS element without additional expenditure. Optionally, without additional process steps, margin terminating structures can be produced parallel to the formation of said active transistor region in the form of circumferential floating rings or of floating field plates.

Claims

1. Power MOS element comprising:

a drift region with a doping of a first doping type;

a channel region with a doping of a second doping type, said second doping type being complementary to said first doping type, and said channel region bordering on said drift region;

a source region with a doping of said first doping type, said source region bordering on said channel region;

a plurality of essentially parallel gate trenches spaced from one another defining an active region of said power MOS element and extending through said source region, said channel region and into said drift region, said gate trenches comprising an electrically conductive material which is electrically insulated from said source region, said channel region and said drift region by an insulator;

a connecting gate trench for connecting the gate trenches in an electrically conductive way, extending through said source region, said channel region and into said drift region, said connecting gate trench comprising an electrically conductive material which is electrically insulated from said source region, said channel region and said drift region by an insulator, said connecting gate trench being a circumferential trench comprising a first connecting region, a second connecting region, a first longitudinal region and a second longitudinal region, said first connecting region connecting first ends of said plurality of gate trenches to one another, said second connecting region connecting second ends of said plurality of gate trenches to one another, and said first and said second longitudinal regions connecting said first and said second connecting regions to each other in such a way that the active region which is defined by said plurality of gate trenches is completely surrounded by said connecting gate trench;

a source contact structure for contacting said source region;

a channel contact structure for contacting said channel region;

a gate contact for contacting said connecting gate trench, said gate contact being connected via a contact hole through said insulator of said connecting gate trench which is filled with an electrically conductive material to said electrically conductive material of said connecting gate trench.

2. Power MOS element according to claim 1 wherein the width of said connecting gate trench for receiving said contact hole is larger than the width of one of said plurality of gate trenches.

3. Power MOS element according to claim 1 wherein the angle between one of said plurality of gate trenches and said connecting gate trench is essentially 90°

.

4. Power MOS element according to claim 1 wherein said gate contact is located at a margin of said power MOS element and only extends partly over an active region of said power MOS element.

5. Power MOS element according to claim 1, further comprising a margin terminating structure completely surrounding an active region of said power MOS element.

6. Power MOS element according to claim 5 wherein said margin terminating structure comprises a plurality of parallel terminating trenches which are not contacted and whose distances between one another increase towards the margin of said power MOS element to fulfil a certain reverse voltage class.

7. Power MOS element according to claim 5 wherein said margin terminating structure comprises a part of a terminating trench which comprises, at its margin opposite to said source region, said drain region and said channel region, a conductive material insulated by an insulator, said conductive material of said margin terminating structure being connected in an electrically conductive way to said source region and said drain region via a contact hole, an upper side metalization and a contact hole, said margin of said power MOS element extending in said terminating trench.

8. Power MOS element according to claim 1 wherein said source contact structure and said channel contact structure comprise a common contact hole filled with an electrically conductive material, said contact hole extending through said source region and into said channel region in such a way that said source region and said channel region can be held at the same potential by means of a single contact.

9. Power MOS element according to claim 1 wherein said drift region, said channel region and said source region are planar layers on a strongly doped substrate layer with a doping of said first doping type.

10. Power MOS element according to claim 1 wherein said drift region, said channel region and said source region are planar layers on a strongly doped substrate layer with a doping of said first doping type.

11. Power MOS element according to claim 8 wherein the margin between said channel region and said source region, due to a contact hole implantation through said contact hole, is not parallel to a main surface of said power MOS element.

13. Power MOS element according to claim 12 wherein the width of said connecting gate trench for receiving said contact hole is larger than the width of one of said plurality of gate trenches.

14. Power MOS element according to claim 12 wherein the angle between one of said plurality of gate trenches and said connecting gate trench is essentially 90°

.

15. Power MOS element according to claim 12 wherein said gate contact is located essentially in the middle of said power MOS element and extends at most partly, if not at all, over an active region of said power MOS element.

16. Power MOS element according to claim 12 wherein said circumferential section of said connecting gate trench comprises two connecting regions which are substantially arranged perpendicularly to said gate trenches, said extension sections being oriented in the same direction as the connecting regions.

17. Power MOS element according to claim 12, having a s rectangular form, said plurality of gate trenches comprising four subgroups, said gate trenches of each subgroup being parallel to a margin of said power MOS element each, and said extension sections of said connecting gate trench each extending diagonally to said rectangles of said power MOS element in the direction of said circumferential connecting gate trench to connect said gate trenches to one another in an electrically conductive way.

18. Power MOS element according to claim 12, further comprising a margin terminating structure completely surrounding an active region of said power MOS element.

19. Power MOS element according to claim 18 wherein said margin terminating structure comprises a plurality of parallel terminating trenches which are not contacted and whose distances between one another increase towards the margin of said power MOS element to fulfil a certain reverse voltage class.

20. Power MOS element according to claim 18 wherein said margin terminating structure comprises a part of a terminating trench which comprises, at its margin opposite to said source region, said drain region and said channel region, a conductive material insulated by an insulator, said conductive material of said margin terminating structure being connected in an electrically conductive way to said source region and said drain region via a contact hole, an upper side metalization and a contact hole, said margin of said power MOS element extending in said terminating trench.

21. Power MOS element according to claim 12 wherein said source contact structure and said channel contact structure comprise a common contact hole filled with an electrically conductive material, said contact hole extending through said source region and into said channel region in such a way that said source region and said channel region can be held at the same potential by means of a single contact.

22. Power MOS element according to claim 12 wherein said drift region, said channel region and said source region are planar layers on a strongly doped substrate layer with a doping of said first doping type.

23. Power MOS element according to claim 12 wherein said drift region, said channel region and said source region are planar layers on a strongly doped substrate layer with a doping of said first doping type.

24. Power MOS element according to claim 21 wherein the margin between said channel region and said source region, due to a contact hole implantation through said contact hole, is not parallel to a main surface of said power MOS element.

26. Method according to claim 25 wherein the steps of photolithographic producing each comprise a step of producing a mask and a step of etching to a specific depth.

27. Method according to claim 25 wherein the step of providing comprises the following steps:

implanting a channel region into a semiconductor substrate which is doped with said first doping type; and

implanting said source region into said semiconductor substrate.

28. Method according to claim 25 wherein the step of is providing a substrate comprises the following steps:

epitaxial growing of said channel region onto a semiconductor substrate;

implanting said source region into said epitaxially grown channel region.

29. Method according to claim 25 wherein, after the step of the photolithographic producing of said gate trenches and said connecting gate trench, at least one purification oxidation with subsequent removal of said purification oxide is carried out.

30. Method according to claim 25 wherein the step of processing said gate trenches and said connecting gate trench comprises the following steps:

carrying out a gate oxidation to produce said insulator;

filling said oxidized trenches with said conductive material;

removing conductive material in such a way that only said conductive material remains in said trenches; and

depositing an intermediate oxide.

31. Method according to claim 30 wherein said intermediate oxide comprises doped or undoped CVC-oxides, such as boron phosphorus silicate glass or silane oxide or combinations of oxide and nitride.

32. Method according to claim 25 wherein, in the step of photolithographic producing and of processing said gate trenches and said connecting gate trench, at least one terminating trench is produced which surrounds an active region of said power MOS element, the active region being established by said plurality of gate trenches and said connecting gate trench.

33. Method according to claim 25 wherein, after the photolithographic producing of said contact holes, a contact hole implantation is carried out to enable a low-resistance contact to said channel region.

34. Method according to claim 25 wherein, after the step of the photolithographic producing of said contact holes, a further contact hole implantation is carried out to modify the doping profile of said channel region and said drift region.

35. Method according to claim 25 wherein said contact holes are filled with a conductive material, whereby said source region and said channel region are short-circuited and said connecting gate trench is contacted.

36. Method according to claim 25 wherein, prior to the photolithographic producing of said gate contact, said source and said channel contacts, a full area metal layer comprising tungsten, aluminium or a combination of tungsten and aluminium is deposited.

37. Method according to claim 25 wherein, in the step of the photolithographic producing of said gate contact, said source contact and said channel contact, a source contact is produced which essentially extends over the whole surface of said power MOS element, except for a region around said connecting gate in which said gate contact is located.

38. Method according to claim 32 wherein, in the step of the photolithographic producing and processing of said gate trenches and said connecting gate trench, a plurality of terminating trenches which are not contacted and whose mutual distance increases towards the margin of said power MOS element is formed.

39. Method according to claim 32 wherein said terminating trench has a width which is 5 to 25 times as big as the width of a gate trench, and wherein, in the step of the photolithographic producing of said contact holes, a contact hole is produced in said source region and said channel region next to said terminating trench and in an electrically conductive material at the margin of said terminating trench, and wherein, in the step of the photolithographic producing of said gate contacts, said source contact and said channel contact, a metallic connection between said contact hole in said terminating trench and said contact hole in said source region and said channel region is produced to produce a field-plate-like structure.

40. Method according to claim 37 wherein said connecting gate trench, said source contact and said gate contact are arranged in such a way that said gate contact is essentially located in the middle of said power MOS element.

41. Method according to claim 25 wherein the step of processing said gate trenches comprises the following substeps:

producing a gate oxide in said gate trenches;

depositing a layer of polysilicon onto said gate oxide;

depositing tungsten onto said polysilicon;

thermal treating of said arrangement in such a way that a silicidation takes place.

42. Method according to claim 25

wherein the step of providing comprises the following steps:

implanting a channel region into a semiconductor substrate which is doped with a first doping type; and

implanting said source region into said semiconductor substrate.

and which, after the step of the photolithographic producing of said gate contact, said source contact and said channel contact, further comprises the following steps;

grinding back said semiconductor substrate on that side which is opposite to the side in which said gate trenches are formed;

implanting a highly doped region into said semiconductor substrate from that side which is ground back; and

depositing a rear side metalization to produce a drain contact.

12. Power MOS element comprising:

a drift region with a doping of a first doping type;

a channel region with a doping of a second doping type, said second doping type being complementary to said first doping type, and said channel region bordering on said drift region;

a source region with a doping of said first doping type, said source region bordering on said channel region;

a plurality of essentially parallel gate trenches spaced from one another defining an active region of the power MOS element and extending through said source region, said channel region and into said drift region, said gate trenches comprising an electrically conductive material which is electrically insulated from said source region, said channel region and said drift region by an insulator;

a connecting gate trench for connecting the gate trenches in an electrically conductive way, extending through said source region, said channel region and into said drift region, said connecting gate trench comprising an electrically conductive material which is electrically insulated from said source region, said channel region and said drift region by an insulator, said connecting gate trench comprising a circumferential section surrounding a non-active region of said power MOS element, in which there are no gate trenches, and extension sections connected in an electrically conductive way to said circumferential section, said extension sections connecting at least a part of the gate trenches to one another in an electrically conductive way;

a source contact structure for contacting said source region;

a channel contact structure for contacting aid channel region;

a gate contact for contacting said connecting gate trench, said gate contact being connected via a contact hole through said insulator of said connecting gate trench which is filled with an electrically conductive material to said electrically conductive material of said connecting gate trench.

25. Method for producing a power MOS element, comprising the following steps:

providing a substrate having a drift region with a doping of a first doping type, a channel region with a doping of a second doping type, said second doping type being complementary to said first doping type and said channel region bordering on said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region;

photolithographic producing of essentially parallel gate trenches spaced from one another defining an active region of the power MOS element, and of a connecting gate trench by means of which said plurality of essentially parallel gate trenches is connectable to one another in an electrically conductive way in such a way that said gate trenches extend through said source region, said channel region and into said drift region,

wherein said connecting gate trench being a circumferential trench comprising a first connecting region, a second connecting region, a first longitudinal region and a second longitudinal region, said first connecting region connecting first ends of said plurality of gate trenches to one another, said second connecting gate trench connecting second ends of said plurality of gate trenches to one another, and said first and said second longitudinal regions connecting said first and said second connecting regions to one another in such a way that the active region which is defined by said plurality of gate trenches is completely surrounded by said connecting gate trench;

or

wherein said connecting gate trench comprising a circumferential section surrounding a non-active region of said power MOS element, in which there are no gate trenches, and extension sections being connected to said circumferential section in an electrically conductive way, said extension sections connecting at least a part of said gate trenches to one another in an electrically conductive way;

processing said gate trenches and said connecting gate trench in order to comprise a conductive material which is isolated from said source region, said channel region and said drift region by an insulator;

photolithographic producing of contact holes for contacting said source region, said channel region and said connecting gate trench, said connecting gate trench being contactable via said contact holes associated to said connecting gate trench;

filling said contact holes with an electrically conductive material; and

photolithographic producing of said gate contact, said source contact and said channel contact.