Semiconductor chip having both polycide and salicide gates and methods for making same
First Claim
1. A method of forming a semiconductor device comprising the steps of:
- forming a polysilicon layer having a first portion and a second portion;
depositing a metal silicide layer on the first portion of the polysilicon layer, but not on the second portion of the polysilicon layer, whereby the first portion of the polysilicon layer becomes a polycide layer; and
depositing a metal layer over the second portion of the polysilicon layer.
6 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor process is provided that creates transistors having polycide gates in a first region of a semiconductor substrate and transistors having salicide gates in a second region of the semiconductor substrate. A polysilicon layer having a first portion in the first region and a second portion in the second region is formed over the semiconductor substrate. Then, a first dielectric layer is formed over the second portion of the polysilicon layer. Metal silicide is deposited over first portion of the polysilicon layer and the first dielectric layer. The metal silicide overlying the first dielectric layer is removed as is the first dielectric layer. The metal silicide and the polysilicon layer are etched to form polycide gates in the first region and polysilicon gates in the second region. A second dielectric layer is formed over the first region. Refractory metal is then deposited over the resulting structure and reacted. As a result, salicide is formed on the polysilicon gates of the second region.
5 Citations
7 Claims
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1. A method of forming a semiconductor device comprising the steps of:
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forming a polysilicon layer having a first portion and a second portion;
depositing a metal silicide layer on the first portion of the polysilicon layer, but not on the second portion of the polysilicon layer, whereby the first portion of the polysilicon layer becomes a polycide layer; and
depositing a metal layer over the second portion of the polysilicon layer. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification