Bidirectional port with clock channel used for synchronization

• US 20030001618A1
• Filed: 06/28/2001
• Published: 01/02/2003
• Est. Priority Date: 06/28/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mooney, Stephen R., Martin, Aaron K., Haycock, Matthew B.
• Granted Patent: US 6,791,356 B2
• Time in Patent Office: Days
• US Class Current: 326/82
• CPC Class Codes: G06F 13/4077 Precharging or discharging

Abstract

A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

Claims

1. A bidirectional port circuit comprising:

a data transceiver;

a clock driver with an enable input node; and

a control circuit to drive the enable input node when the data transceiver is initialized.

2. The bi-directional port circuit of claim 1 further comprising a clock receiver circuit having a clock detection circuit to detect the presence of an incoming clock signal.

3. The bi-directional port circuit of claim 2 wherein the data transceiver comprises:

a voltage mode output driver having an output node; and

a data receiver having an input node coupled to the output node of the voltage mode driver.

4. The bi-directional port circuit of claim 2 wherein the data transceiver comprises:

a current mode output driver having a differential output node; and

a data receiver having a differential input node coupled to the differential output node of the current mode driver.

5. The bi-directional port circuit of claim 2 wherein the control circuit comprises an initialization circuit to initialize the data transceiver.

6. The bi-directional port circuit of claim 5 wherein the initialization circuit comprises an impedance control circuit.

7. The bi-directional port circuit of claim 6 wherein the control circuit is operative to enable the clock driver when the impedance control circuit has initialized an impedance of the data transceiver.

8. The bi-directional port circuit of claim 7 wherein:

the data transceiver includes a voltage mode driver having an output impedance; and

the impedance initialized by the impedance control circuit is the output impedance of the voltage mode driver.

9. The bi-directional port circuit of claim 7 wherein:

the data transceiver includes a current mode driver having at least one termination resistor; and

the impedance initialized by the impedance control circuit is the at least one termination resistor.

10. The bi-directional port circuit of claim 5 wherein:

the data transceiver includes a variable current source circuit; and

the initialization circuit is operative to initialize the variable current source circuit.

11. The bidirectional port circuit of claim 5 wherein:

the data transceiver includes a receiver circuit having a variable offset; and

the initialization circuit is operable to initialize the variable offset of the receiver circuit.

13. The integrated circuit of claim 12 wherein the output driver is a voltage mode driver with a programmable output impedance.

14. The integrated circuit of claim 13 wherein the initialization circuit comprises an impedance control circuit to initialize the programmable output impedance.

15. The integrated circuit of claim 13 further comprising a clock receiver circuit to receive an inbound clock signal from an inbound clock node external to the integrated circuit.

16. The integrated circuit of claim 15 wherein the clock receiver circuit comprises a clock detection circuit to detect whether a signal is present on the inbound clock node external to the integrated circuit.

17. The integrated circuit of claim 15 further comprising a data receiver to receive a data signal on the data node external to the data circuit.

18. The integrated circuit of claim 12 wherein:

the output driver is a current mode driver with a variable current source; and

the initialization circuit is operative to initialize the variable current source.

19. The integrated circuit of claim 12 wherein:

the output driver is a current mode driver with a variable termination resistor; and

the initialization circuit is operative to initialize the variable termination resistor.

20. The integrated circuit of claim 19 further comprising a clock receiver circuit to receive an inbound clock signal from an inbound clock node external to the integrated circuit.

21. The integrated circuit of claim 20 wherein the clock receiver circuit comprises a clock detection circuit to detect whether a signal is present on the inbound clock node external to the integrated circuit.

22. The integrated circuit of claim 20 further comprising a data receiver to receive a data signal on the data node external to the data circuit.

23. The integrated circuit of claim 22 further comprising a processor coupled to the data output driver, the enable node of the clock driver, and the clock detect node of the clock detection circuit.

24. The integrated circuit of claim 12 wherein the integrated circuit is a circuit type from the group comprising:

a processor, a processor peripheral, a memory, and a memory controller.

26. The electronic system of claim 25 wherein the first data driver has a programmable output impedance, and the initialization circuit of the first integrated circuit is operative to set the programmable output impedance.

27. The electronic system of claim 25 wherein the first data driver has a programmable current source, and the initialization circuit of the first integrated circuit is operative to set the programmable current source.

28. The electronic system of claim 25 wherein the first data driver has a programmable slew rate, and the initialization circuit of the first integrated circuit is operative to set the programmable slew rate.

29. The electronic system of claim 25 wherein the first data driver has a programmable termination resistor, and the initialization circuit of the first integrated circuit is operative to set the programmable termination resistor.

30. The electronic system of claim 25 wherein the first data receiver has a programmable offset, and the initialization circuit of the first integrated circuit is operative to set the programmable offset.

12. An integrated circuit comprising:

an output driver to drive a data signal on a data node external to the integrated circuit;

an initialization circuit to initialize the output driver; and

a clock driver responsive to the initialization circuit such that the clock driver drives an outbound clock signal off the integrated circuit when the output driver is initialized.

25. An electronic system comprising:

a first integrated circuit having a first simultaneous bidirectional port comprising a first data driver, a first data receiver, a first clock driver with a first enable input node, and a first clock receiver with a first clock detect circuit; and

a second integrated circuit having a second simultaneous bidirectional port comprising a second data driver, a second data receiver, a second clock driver with a second enable input node, and a second clock receiver with a second clock detect circuit;

wherein output nodes of the first and second data drivers are coupled in common with input nodes of the first and second data receivers, the first and second integrated circuits include initialization circuits, and the first and second enable input nodes are coupled to the initialization circuits to enable clock signals after the first and second simultaneous bidirectional ports are initialized.