Apparatus and method for communication link receiver having adaptive clock phase shifting

• US 20030002608A1
• Filed: 06/30/2001
• Published: 01/02/2003
• Est. Priority Date: 06/30/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Glenn, Robert C., Kelly, Neil P.
• Granted Patent: US 7,167,533 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H04L 7/0037 Delay of clock signal
• CPC Class Codes: H04L 7/0041 Delay of data signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A method that involves imposing different delays upon a received clock signal in order to generate a plurality of clocks. Then, providing a plurality of data streams by sampling a received data signal with each of the plurality clocks. The plurality of clocks each have a different phase position within an eye pattern of the received data signal as a result of the different imposed delays. The phase positions of the clocks are then moved into an opening of the eye pattern if differences in the plurality of data streams indicate one of the phase positions is not within the eye pattern opening. Various aparatti that perform the method are also described.

Claims

1. An apparatus, comprising:

a) a clock generator that imposes different delays upon a received clock signal in order to generate a plurality of clocks;

b) a data sampler that provides a plurality of data streams by sampling a received data signal with each of said plurality clocks, said plurality of clocks each having a different phase position within an eye pattern of said received data signal as a result of said different imposed delays; and

c) a phase adjust unit that moves said phase positions of said clocks into an opening of said eye pattern if differences in said plurality of data streams indicate one of said phase positions is not within said eye pattern opening.

2. The apparatus of claim 1 wherein one of said data streams is an output data stream that represents an interpretation of said received data signal.

3. The apparatus of claim 1 wherein said plurality of clocks further comprises three clocks such that said plurality of phase positions further comprises a middle phase position and a pair of outer phase positions.

4. The apparatus of claim 3 wherein said middle phase position is designed to be midway between said pair of outer phase positions.

5. The apparatus of claim 3 wherein an output data stream that represents an interpretation of said received data signal is produced with said clock having said middle phase position.

6. The apparatus of claim 1 further comprising a phase shifter that shifts said received clock signal phase position in response to a control signal from said phase adjust unit.

7. The apparatus of claim 6 further comprising a filter that provides a voltage, said voltage corresponding to said control signal.

8. The apparatus of claim 6 further comprising a filter that provides a digital output, said digital output corresponding to said control signal.

9. The apparatus of claim 1 further comprising a phase shifter that shifts said received data signal phase position in response to a control signal from said phase adjust unit.

10. A method, comprising:

a) imposing different delays upon a received clock signal in order to generate a plurality of clocks;

b) providing a plurality of data streams by sampling a received data signal with each of said plurality clocks, said plurality of clocks each having a different phase position within an eye pattern of said received data signal as a result of said different imposed delays; and

c) moving said phase positions of said clocks into an opening of said eye pattern if differences in said plurality of data streams indicate one of said phase positions is not within said eye pattern opening.

11. The method of claim 10 wherein one of said data streams is an output data stream that represents an interpretation of said received data signal.

12. The method of claim 10 wherein said plurality of clocks further comprises three clocks such that said plurality of phase positions further comprises a middle phase position and a pair of outer phase positions.

13. The method of claim 12 wherein said middle phase position is designed to be midway between said pair of outer phase positions.

14. The method of claim 12 further comprising producing an output data stream that represents an interpretation of said received data signal by sampling said data signal with said clock having said middle phase position.

15. The method of claim 10 wherein said moving further comprises shifting said received clock signal phase position in response to a control signal.

16. The method of claim 15 further comprising driving a stream of current pulses through a filter in order to provide a voltage, said voltage corresponding to said control signal.

17. The method of claim 15 further comprising driving a stream of digital words through a digital filter in order to provide a digital filter output, said digital filter output corresponding to said control signal.

18. The method of claim 10 wherein said moving further comprises shifting said received data signal phase position in response to a control signal.

20. The apparatus of claim 19 wherein one of said data streams is an output data stream that represents an interpretation of said received data signal.

21. The apparatus of claim 19 wherein said plurality of clocks further comprises three clocks such that said plurality of phase positions further comprises a middle phase position and a pair of outer phase positions.

22. The apparatus of claim 21 wherein said middle phase position is designed to be midway between said pair of outer phase positions.

23. The apparatus of claim 19 further comprising a phase shifter that shifts said received clock signal phase position in response to a control signal from said phase adjust unit.

24. The apparatus of claim 23 further comprising a filter that provides a voltage, said voltage corresponding to said control signal.

25. The apparatus of claim 19 further comprising a phase shifter that shifts said received data signal phase position in response to a control signal from said phase adjust unit.

19. An apparatus, comprising:

a) a transmitting unit that transmits a data signal and a clock signal;

b) a receiving unit that receives said data signal and said clock signal, said receiving unit further comprising;

1) a clock generator that imposes different delays upon said received clock signal in order to generate a plurality of clocks;

2) a data sampler that provides a plurality of data streams by sampling said received data signal with each of said plurality clocks, said plurality of clocks each having a different phase position within an eye pattern of said received data signal as a result of said different imposed delays; and

3) a phase adjust unit that moves said phase positions of said clocks into an opening of said eye pattern if differences in said plurality of data streams indicate one of said phase positions is not within said eye pattern opening.