Manufacturing method of the semiconductor device

• US 20030003724A1
• Filed: 06/07/2002
• Published: 01/02/2003
• Est. Priority Date: 06/27/2001
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Uchiyama, Hiroyuki, Shiota, Takashi
• Granted Patent: US 6,746,938 B2
• Time in Patent Office: Days
• US Class Current: 438/667
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/8252 the substrate being a semiconductor, using III-V technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

A method manufactures a semiconductor device by forming at least an active device on a principal surface of a semiconductor substrate; etching the semiconductor substrate to thereby form a viahole adjacent to an active region where the active device is formed; and forming a plated wiring including the inner wall of the viahole and extending to an electrode of the active device on the surface of the substrate. This method uses a photo sensitive polyimide material as an etching mask in the step of forming a viahole and can thereby form a fine viahole in a high yield.

Claims

1. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming at least an active device on a principal surface of a semiconductor substrate;

etching the semiconductor substrate to thereby form a viahole adjacent to an active region where the active device is formed; and

forming a plated wiring, the plated wiring including an inner wall of the viahole and extending to an electrode of the active device on the surface of the substrate,

wherein a photo sensitive polyimide material is used as an etching mask in the step of forming a viahole.

2. The method according to claim 1 wherein the step of forming a viahole comprises the step of etching the semiconductor substrate from the surface of the substrate on which the active device is formed.

3. The method according to claim 1 wherein the step of forming a viahole comprises the step of etching the semiconductor substrate from the back side of the substrate opposite to the surface on which the active device is formed.

4. The method according to claim 1 wherein the semiconductor substrate comprises a substrate including a multi-layer epitaxial film of III-V compound semiconductor.

5. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming at least an active device on a principal surface of a semiconductor substrate;

etching the semiconductor substrate with the use of a photo sensitive polyimide material as an etching mask from the surface of the substrate on which the active device is formed to thereby form a viahole adjacent to an active region where the active device is formed;

forming a plated wiring, the plated wiring including an inner wall of the viahole and extending to an electrode of the active device on the surface of the substrate;

reversing the substrate and temporarily fixing the reversed substrate on a base wafer with an adhesive;

grinding or polishing the back side of the semiconductor substrate temporarily fixed on the base wafer to thereby thin the substrate;

subjecting the thinned substrate to wet etching to thereby make the plated wiring at the inside bottom of the viahole open; and

separating the semiconductor substrate carrying the viahole from the base wafer.

6. The method according to claim 5 wherein the semiconductor substrate comprises a substrate including a multi-layer epitaxial film of III-V compound semiconductor.

7. A method of manufacturing a semiconductor device, the method comprising the steps of:

forming at least an active device on a principal surface of a semiconductor substrate;

etching the semiconductor substrate with the use of a photo sensitive polyimide material as an etching mask from the surface of the substrate on which the active device is formed to thereby form a viahole adjacent to an active region where the active device is formed;

forming a plated wiring, the plated wiring including the inner wall of the viahole and extending to an electrode of the active device on the surface of the substrate;

reversing the substrate and temporarily fixing the reversed substrate on a base wafer with an adhesive;

grinding or polishing the back side of the semiconductor substrate temporarily fixed on the base wafer to thereby thin the substrate;

etching the thinned substrate with the use of a photo sensitive polyimide material as an etching mask in a region to be a viahole and a region directly underneath the active device on the surface of the substrate from the back side of the substrate to make the plated wiring at the inside bottom of the viahole open to thereby form a viahole structure and a heat-sink structure in one process step;

plating a metal on overall of the back side of the substrate to thereby form a plated metal layer; and

separating the semiconductor substrate carrying the viahole from the base wafer.