Simultaneous dual rail static carry-save-adder circuit

• US 20030005017A1
• Filed: 05/24/2001
• Published: 01/02/2003
• Est. Priority Date: 05/24/2001
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Philhower, Robert Alan, Bradley, Douglas Hooker, Cao, Tai Anh
• Granted Patent: US 6,785,703 B2
• Time in Patent Office: Days
• US Class Current: 708/700
• CPC Class Codes: G06F 7/5016 forming at least one of the output signals directly from the minterms of the input signals, i.e. with a minimum number of gate levels

Abstract

An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is one at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry_— signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry_— signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.

Claims

1. A static circuit for generating an arithmetic output, comprising:

a first set of devices having a first switching characteristic; and

a second set of devices, having a second switching characteristic, symmetrically connected to said first set;

wherein said arithmetic output and a complement thereof are provided concurrently on respective output nodes of said circuit.

2. A circuit according to claim 1 wherein each one of the first set of devices is associated with a corresponding one of the second set of devices and said associated devices are both on, or off at the same time.

3. A circuit according to claim 2 wherein the first set of devices are P type transistors and the second set of devices are N type transistors.

4. A circuit according to claim 1 wherein each one of the first set of devices is associated with a corresponding one of the second set of devices and at least one of said associated first or second devices is turned on, while the other of said first or second devices is turned off.

5. A circuit according to claim 4 wherein the first set of devices are P type transistors and the second set of devices are N type transistors.

13. A method according to claim 1, further comprising the steps of:

associating each one of the first set of devices with a corresponding one of the second set of devices; and

causing at least one of said associated first or second devices to be on, while the other of said first or second devices is turned off.

14. A method according to claim 4 wherein the first set of devices are P type transistors and the second set of devices are N type transistors.

6. A data processing system, comprising:

a memory;

a central processing unit;

at least one execution unit included within said central processing unit for performing arithmetic and logical operations;

an arithmetic circuit within said at least one execution unit which performs arithmetic operations on data stored in said memory;

at least one adder circuit included in said arithmetic circuit that receives plural input signals and generates a sum thereof;

wherein said at least one adder includes a static circuit for generating an arithmetic output, including;

a first set of devices having a first switching characteristic;

a second set of devices, having a second switching characteristic, symmetrically connected to said first set such that said output and a complement thereof are provided concurrently on respective output nodes of said circuit.

7. A system according to claim 6 wherein each one of the first set of devices is associated with a corresponding one of the second set of devices and said associated devices are both on, or off at the same time.

8. A system according to claim 6 wherein each one of the first set of devices is associated with a corresponding one of the second set of devices and at least one of said associated first or second devices is turned on, while the other of said first or second devices is turned off.

9. A system according to claim 6 wherein said first set of devices are P type transistors and said second set of devices are N type transistors.

11. A method according to claim 8, further comprising the steps of:

associating each one of the first set of devices with a corresponding one of the second set of devices; and

causing said associated devices to be both turned on, or both turned off at the same time.

12. A method according to claim 9 wherein the first set of devices are P type transistors and the second set of devices are N type transistors.

16. A system according to claim 15 wherein each one of the first set of devices is associated with a corresponding one of the second set of devices and at least one of said associated first or second devices is turned on, while the other of said first or second devices is turned off.

17. A system according to claim 16 wherein said first set of devices are P type transistors and said second set of devices are N type transistors.

19. A circuit according to claim 19 wherein the first set of devices are P type transistors and the second set of devices are N type transistors.

10. A method of generating an arithmetic output from a static circuits, said method comprising the steps of:

providing a first set of devices having a first switching characteristic; and

symmetrically connecting a second set of devices, having a second switching characteristic, to said first set of devices;

wherein said arithmetic output and a complement thereof are provided concurrently on respective output nodes of said circuit.

15. A data processing system, comprising:

a memory;

a central processing unit;

at least one execution unit included within said central processing unit for performing arithmetic and logical operations;

an arithmetic circuit within said at least one execution unit which performs arithmetic operations on data stored in said memory;

at least one adder circuit included in said arithmetic circuit that receives plural input signals and generates a sum and a carry output thereof;

wherein said at least one adder includes a static circuit for generating an arithmetic output, including;

a first set of devices having a first switching characteristic;

a second set of devices, having a second switching characteristic, symmetrically connected to said first set such that said output and a complement thereof are provided concurrently on respective output nodes of said circuit;

wherein each one of the first set of devices is associated with a corresponding one of the second set of devices and said associated devices are both on, or off at the same time.

18. A transmission gate circuit for generating an arithmetic output, comprising:

a first set of devices having a first switching characteristic; and

a second set of devices, having a second switching characteristic, symmetrically connected to said first set;

wherein each one of the first set of devices is associated with a corresponding one of the second set of devices and said associated devices are both on, or off at the same time;

wherein said arithmetic output and a complement thereof are provided concurrently on respective output nodes of said circuit.