Imprecise snooping based invalidation mechanism

• US 20030005236A1
• Filed: 06/29/2001
• Published: 01/02/2003
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Arimilli, Ravi Kumar, Guthrie, Guy Lynn, Lewis, Jerry Don, Dodson, John Steven
• Granted Patent: US 6,801,984 B2
• Time in Patent Office: Days
• US Class Current: 711/146
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means

Abstract

A method, system, and processor cache configuration that enables efficient retrieval of valid data in response to an invalidate cache miss at a local processor cache. A cache directory is enhanced by appending a set of directional bits in addition to the coherency state bits and the address tag. The directional bits provide information that includes the processor cache identification (ID) and routing method. The processor cache ID indicates which processor operation resulted in the cache line of the local processor changing to the invalidate (I) coherency state. The processor operation may be issued by a local processor or by a processor from another group or node of processors if the multiprocessor system comprises multiple nodes of processors. The routing method indicates what transmission method to utilize to forward a request for the cache line. The request may be forwarded to a local system bus or directly to another processor group via a switch or broadcast mechanism. Processor/Cache directory logic is provided to set and interpret the values of the directional bits and provide responses depending on the values of the bits.

Claims

1. A method for providing directed system response to an invalidation miss at a local processor cache of a data processing system having a plurality of processors, said method comprising:

providing directional bits for a cache line of a cache directory of said local processor cache;

in response to a snoop of an operation that causes a coherency state of said cache line in said local processor cache to go invalid, setting a value of said directional bits to indicate a processor identifier (ID) associated with an origination processor that issued said operation.

2. The method of claim 1, further comprising, responsive to a request for said cache line by an associated local processor, immediately forwarding said request to a processor indicated by said processor ID, whereby said request is forwarded to said origination processor.

3. The method of claim 3, wherein said directional bits includes at least one source bit that is utilized to stored said processor ID and at least one route bit that is utilized to indicate a transfer method for forwarding said request for said cache line, wherein said forwarding step further comprises:

responsive to a request for said cache line by an associated local processor, immediately forwarding said request to said origination processor via a transfer mechanism indicated by said at least one route bit.

4. The method of claim 3, wherein said immediately forwarding step includes first retrieving said processor ID and said routing information from said plurality of bits.

5. The method of claim 4, wherein said multiprocessor data processing system comprises at least two nodes of processor groups, and said forwarding of said request includes:

first determining that said origination processor belongs to a local processor group that includes said local processor; and

in response to said determining step, setting said value of said at least one route bit to indicate forwarding via a local transmission mechanism.

6. The method of claim 5, wherein when said local processor is connected via a switch to other processors within said local processor group, said request is forwarded directly to said origination processor, and when said local processor is connected via a local system bus, said request is broadcasted on said local system bus.

7. The method of claim 6, further comprising setting said value of said route bit to indicate a global, system-wide bus broadcast when said processor does not belong to said local group.

8. The method of claim 6, further comprising setting said value of said routing method to indicate a directed, system-wide bus broadcast when said processor does not belong to said local group and said processor groups are connected via a switch, wherein a specific processor from another processor group is sent the request directly.

9. The method of claim 8, further comprising, responsive to a cache miss when said request is transmitted directly to said origination processor, issuing said request to said global system bus.

10. The method of claim 9, wherein said forwarding further includes:

storing a value of a closest processor having a valid copy of said cache line within said source bit when more than one processor has a valid copy of said cache line; and

subsequently forwarding said request to said closest processor.

11. A multiprocessor data processing system that provides directed addressing of cache intervention in response to an invalidate, comprising:

a plurality of processors, each processor having an associated cache that supports intervention;

logic associated with a cache directory of at least one local processor cache that;

responsive to a snoop of an operation that invalidates a cache line of said local processor cache, updates a directory entry of said cache line to include a processor identifier (ID) of the origination processor, which issued said operation; and

responsive to a later request from a local processor to access said cache line, immediately forwards said request to a processor indicated by said processor ID, whereby said request is forwarded to said origination processor.

12. The multiprocessor data processing system of claim 11, wherein said logic further provides source routing information for said directory entry that is utilized to indicate a transfer method for forwarding said request for said cache line, wherein said logic forwards said request to said origination processor via a transfer mechanism indicated by said source routing information.

13. The multiprocessor data processing system of claim 12, further comprising at least two nodes of processor groups, and said logic further includes:

means for first determining that said origination processor belongs to a local processor group that includes said local processor; and

means, responsive to said determining step, for setting said value of said at least one route bit to indicate forwarding via a local transmission mechanism.

14. The multiprocessor data processing system of claim 13, wherein when said local processor is connected via a switch to other processors within said local processor group, said request is forwarded directly to said origination processor, and when said local processor is connected via a local system bus, said request is broadcasted on said local system bus.

15. The multiprocessor data processing system of claim 14, wherein said logic further comprises means for setting said value of said route bit to indicate a global, system-wide bus broadcast when said processor does not belong to said local group.

16. The multiprocessor data processing system of claim 15, wherein said logic further comprises means for setting said value of said routing method to indicate a directed, system-wide bus broadcast when said processor does not belong to said local group and said processor groups are connected via a switch, wherein a specific processor from another processor group is sent the request directly.

17. The multiprocessor data processing system of claim 16, wherein said logic further comprises means, responsive to a cache miss when said request is transmitted directly to said origination processor, for issuing said request to said global system bus.

18. The multiprocessor data processing system of claim 17, wherein said forwarding means further includes means for storing a value of a closest processor having a valid copy of said cache line within said source bit when more than one processor has a valid copy of said cache line.

20. The memory subsystem of claim 19, wherein said logic includes:

means, responsive to a snoop of an operation that invalidates a cache line of said local processor cache, for updating a directory entry of said cache line to include a processor identifier (ID) of the origination processor, which issued said operation; and

means, responsive to a later request from a local processor to access said cache line, for immediately forwarding said request to a processor indicated by said processor ID, whereby said request is forwarded to said origination processor.

21. The memory subsystem of claim 20, wherein said logic further provides source routing information for said directory entry that is utilized to indicate a transfer method for forwarding said request for said cache line, wherein said logic forwards said request to said origination processor via a transfer mechanism indicated by said source routing information.

22. The memory subsystem of claim 21, wherein said multiprocessor data processing system comprising at least two nodes of processor groups, and said logic further includes:

means for first determining that said origination processor belongs to a local processor group that includes said local processor; and

means, responsive to said determining step, for setting said value of said at least one route bit to indicate forwarding via a local transmission mechanism.

23. The memory subsystem of claim 22, wherein when said local processor is connected via a switch to other processors within said local processor group, said request is forwarded directly to said origination processor, and when said local processor is connected via a local system bus, said request is broadcasted on said local system bus.

24. The memory subsystem of claim 23, wherein said logic further comprises means for setting said value of said route bit to indicate a global, system-wide bus broadcast when said processor does not belong to said local group.

25. The memory subsystem of claim 24, wherein said logic further comprises means for setting said value of said routing method to indicate a directed, system-wide bus broadcast when said processor does not belong to said local group and said processor groups are connected via a switch, wherein a specific processor from another processor group is sent the request directly.

26. The memory subsystem of claim 25, wherein said logic further comprises means, responsive to a cache miss when said request is transmitted directly to said origination processor, for issuing said request to said global system bus.

27. The memory subsystem of claim 26, wherein said forwarding means further includes means for storing a value of a closest processor having a valid copy of said cache line within said source bit when more than one processor has a valid copy of said cache line.

19. A memory subsystem of a multiprocessor data processing system comprising:

a memory;

a plurality of caches associated with processors of said multiprocessor data processing system that comprise cache lines in which data is stored;

a plurality of cache directories each affiliated with a particular one of said plurality of caches, wherein each entry of said cache directory includes a coherency state for each cache line within said particular cache, an address tag, and directional bits, which indicates an origination processor whose cache contains a valid copy of data when said coherency state of said cache line is the invalidate state, wherein an operation that caused said cache line to be invalidated was issued by the origination processor; and

logic, responsive to a receipt of a request for said cache line, for forwarding a request for said cache line from an associated local processor to an origination processor indicated by said directional bits.