Method and apparatus for a digital clock multiplication circuit

• US 20030006850A1
• Filed: 05/21/2002
• Published: 01/09/2003
• Est. Priority Date: 04/25/2000
• Status: Active Grant

• Current Assignee: National University of Singapore
• Original Assignee: National University of Singapore
• Inventors: Lye, Kin Mun, Joe, Jurianto
• Granted Patent: US 6,661,298 B2
• Time in Patent Office: Days
• US Class Current: 331/100
• CPC Class Codes: H03K 5/00006 Changing the frequency modulating pulses H03K7/00; frequency dividers H03K21/00 - H03K29/00; additive or subtractive mixing of two pulse rates into one G06F7/605; pulse rate dividers G06F7/68

Abstract

A clock multiplication technique includes driving two oscillatory circuits by an input signal. One of the circuits has an inverted input. The oscillatory circuits are characterized by a transfer function having an unstable region bounded by two stable region. Oscillations produced during operation of each of the circuits in the unstable regions are combined to produce a signal whose frequency is a multiple of the input frequency.

Claims

1. A method for frequency multiplication of an input signal having a first signal level and a second signal level and a first frequency, comprising:

producing a first intermediate signal having m oscillations during the first half of a first cycle of said input signal and no oscillations during the second half of said first cycle, including feeding said input signal to an input of a first oscillation circuit;

producing a second intermediate signal having no oscillations during the first half of said first cycle and having n oscillations during a second half cycle of said first cycle, including inverting said input signal to produce an inverted signal and feeding said inverted signal to an input of a second oscillation circuit; and

combining said first and second intermediate signals to produce an output signal having a second frequency that is a multiple of said first frequency,

each said oscillation circuit having an operating point which varies depending on the level of the signal at its input, each said oscillation circuit further having a transfer function characterized by having an unstable operating region bounded by a first stable operating region and a second stable operating region so that said circuit produces oscillatory output when said operating point is varied into said unstable region and said circuit has a non-oscillatory output when said operating point is varied into either of said first and second stable regions.

2. The method of claim 1 wherein m is not equal to n.

3. The method of claim 1 wherein m is equal to n.

4. The method of claim 1 wherein m+n is an odd number.

5. The method according to claim 1 wherein:

said operating point of said first oscillation circuit is forced into said unstable region to produce at least one oscillation when said input signal is at said first signal level, and said operating point is forced to vary into either one of said stable operating regions in order to terminate said at least one oscillation when said input signal is at said second signal level; and

said operating point of said second oscillation circuit is forced into said unstable region to produce at least one oscillation when said inverted signal is at said first signal level, and said operating point is forced to vary into either one of said stable operating regions in order to terminate said at least one oscillation when said inverted signal is at said second signal level.

6. The method of claim 1 wherein said combining includes feeding said first and second intermediate signals into inputs of a summing circuit.

7. The method of claim 1 wherein said combining includes feeding said first and second intermediate signals into inputs of an OR gate.

8. The method according to claim 1 wherein one of said oscillation circuits includes an operational amplifier circuit with feedback, said one of said oscillation circuits having a series input through an inductor, wherein said unstable operating region is a negative resistance region, and wherein said operating point is forced into said unstable region by a changing voltage applied to said inductor;

and

wherein the other of said oscillation circuits includes an element having negative impedance, said other oscillation circuit having a series input through an inductor, wherein said unstable operating region is a negative impedance region, and wherein said operating point is forced into said unstable region by a changing current applied through said inductor.

9. The method according to claim 8 wherein said element is a tunnel diode.

10. The method according to claim 1 wherein at least one of said oscillation circuits includes an operational amplifier circuit with feedback, said at least one of said oscillation circuits having a series input through an inductor, wherein said unstable operating region is a negative resistance region, and wherein said operating point is forced into said unstable region by a changing voltage applied to said inductor.

11. The method according to claim 1 wherein at least one of said oscillation circuits includes an element having negative impedance, said at least one of said oscillation circuits having a series input through an inductor, wherein said unstable operating region is a negative impedance region, and wherein said operating point is forced into said unstable region by a changing current applied through said inductor.

12. The method according to claim 11 wherein said element is a tunnel diode.

14. The circuit according to claim 13 wherein said operating point of said first oscillation circuit is forced into said unstable region to produce at least one oscillation upon receiving a signal that is at said first signal level, and said operating point is forced to vary into either one of said stable operating regions in order to terminate said at least one oscillation upon receiving a signal that is at said second signal level;

and said operating point of said second oscillation circuit is forced into said unstable region to produce at least one oscillation upon receiving a signal that is at said first signal level, and said operating point is forced to vary into either one of said stable operating regions in order to terminate said at least one oscillation upon receiving a signal that is at said second signal level.

15. The circuit according to claim 13 wherein said combining circuit is a summing circuit.

16. The circuit according to claim 13 wherein said combining circuit is an OR gate.

17. The circuit according to claim 13 wherein one of said first and said second oscillation circuits includes a first negative impedance element, wherein said unstable operating region is a first negative impedance region, and wherein said operating point is forced into said unstable region by the signal level of a received signal;

and

wherein the other of said first and said second oscillation circuits includes a second negative impedance element, said oscillation circuit having a series input through an inductor, wherein said unstable operating region is a negative impedance region, and wherein said operating point is forced into said unstable region by a changing current applied through said inductor.

18. The circuit according to claim 17 wherein said second negative impedance element is a tunnel diode.

19. The circuit according to claim 18 wherein said oscillation circuits each includes a negative impedance element, wherein said unstable operating region is a negative impedance region, and wherein said operating point is forced into said unstable region by the signal level of a received signal.

20. The circuit according to claim 18 wherein said oscillation circuits each includes a negative impedance element, said oscillation circuits each having a series input through an inductor, wherein said unstable operating region is a negative impedance region, and wherein said operating point is forced into said unstable region by a changing current applied through said inductor.

21. The circuit according to claim 20 wherein said element is a tunnel diode.

13. A frequency multiplication circuit comprising:

a signal input terminal for receiving an input signal having a first frequency, said input signal having a first signal level and a second signal level;

a first oscillation circuit having an input coupled to receive a signal from said signal input terminal, and further having an output;

an inverter circuit having an input coupled to receive a signal from said signal input terminal, and further having an output;

a second oscillation circuit having an input coupled to receive an inverted signal from said output of said inverter circuit, and further having an output; and

a combining circuit having an input coupled to receive signals from said outputs of said oscillation circuits, said combining circuit further having a signal output terminal,

each said oscillation circuit configured so that its transfer function has an unstable operating region bounded by a first stable operating region and by a second stable operating region, said transfer function defining a set of operating points, said operating points being dependent on the signal level at said oscillation circuit input,

each said oscillation circuit further configured to produce oscillatory output when said operating point is varied into said unstable region, each said oscillation circuit further adapted to produce a non-oscillatory output when said operating point is varied into either of said first and second stable regions.

22. A digital system comprising:

first digital circuitry; and

second digital circuitry operatively coupled to said first digital circuitry, said second digital circuitry including a digital clock multiplier,

said digital clock multiplier comprising;

a clock input terminal for receiving a clock signal having a first frequency, said clock signal having a first signal level and a second signal level;

a first oscillation circuit having an input coupled to receive a signal from said clock input terminal, and further having an output;

an inverter circuit having an input coupled to receive a signal from said clock input terminal, and further having an output;

a second oscillation circuit having an input coupled to receive an inverted signal from said output of said inverter circuit, and further having an output; and

a combining circuit having an input coupled to receive signals from said outputs of said oscillation circuits, said combining circuit further having a clock output terminal,

each said oscillation circuit having a transfer function, said transfer function having an unstable operating region bounded by a first stable operating region and by a second stable operating region, said transfer function defining a set of operating points of each said oscillation circuit, each said oscillation circuit adapted to produce oscillatory output when said operating point is varied into said unstable region, each said oscillation circuit further adapted to produce a non-oscillatory output when said operating point is varied into either of said first and second stable regions.

23. The system of claim 22 wherein said operating point of said first oscillation circuit is forced into said unstable region to produce at least one oscillation upon receiving a signal that is at said first signal level, and said operating point is forced to vary into either one of said stable operating regions in order to terminate said at least one oscillation upon receiving a signal that is at said second signal level;

and said operating point of said second oscillation circuit is forced into said unstable region to produce at least one oscillation upon receiving a signal that is at said first signal level, and said operating point is forced to vary into either one of said stable operating regions in order to terminate said at least one oscillation upon receiving a signal that is at said second signal level.

24. The circuit according to claim 22 wherein said combining circuit is an OR gate.

26. The method of claim 25 wherein m is not equal to n.

27. The method of claim 25 wherein m is equal to n.

28. The method of claim 25 wherein (m+n) is an odd number.

25. A method for frequency multiplication of an input signal by a factor of (m+n), comprising:

producing a first signal having m oscillations during the first half of a first cycle of said input signal and no oscillations during the second half of said first cycle;

producing a second signal having no oscillations during the first half of said first cycle and having n oscillations during a second half cycle of said first cycle; and

combining said first and second signals to produce a third signal that has a frequency of (m+n) times the frequency of said input signal.