METHOD FOR FABRICATING MULTI-LAYERED SUBSTRATES

• US 20030008475A1
• Filed: 01/04/2000
• Published: 01/09/2003
• Est. Priority Date: 01/08/1999
• Status: Active Grant

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: KOROLIK, MIKHAIL, CHEUNG, NATHAN W., EN, WILLIAM G., FARRENS, SHARON N.
• Granted Patent: US 6,534,381 B2
• Time in Patent Office: Days
• US Class Current: 438/455
• CPC Class Codes: H01L 21/76251 using bonding techniques

Abstract

A method for forming a multi-layered substrate. The method includes forming a compliant layer on a face of a first substrate (10). Joining the compliant layer against a face of a second substrate (20), where the compliant layer forms around a surface non-uniformity on the second substrate face.

Claims

1. A method for fabricating a substrate, said method comprising:

providing a first substrate having a substantially planar surface, said first substrate being of a first substrate type;

implanting particles into said substantially planar surface to a selected depth to define a volume of implanted material within said first substrate, said volume of implanted material having an amorphous characteristic from said selected depth to said substantially planar surface;

contacting a face of a second substrate against said substantially planar implanted surface, said contacting bonding said face to said substantially planar surface;

wherein said implanted material provides a compliant layer for embedding a surface non-uniformity into said compliant layer to facilitate bonding of said face to said substantially planar surface.

2. The method of claim 1 wherein said first substrate comprises a silicon substrate.

3. The method of claim 1 wherein said second substrate comprises a silicon substrate.

4. The method of claim 1 wherein said volume comprises a depth of about 1000 Angstroms and less.

5. The method of claim 1 wherein said particles comprise silicon bearing ions.

6. The method of claim 1 further comprising a step of annealing said contacted first substrate and said second substrate to further attach said face to said substantially planar surface.

7. The method of claim 6 wherein said annealing is maintained at a temperature of less than about 200 degrees Celsius.

8. The method of claim 6 wherein said annealing is maintained at a temperature of less than about 100 degrees Celsius.

9. The method of claim 1 wherein said substantially planar surface comprises an average surface roughness in the range of 10 angstroms and less.

10. The method of claim 1 wherein said implanted substantially planar surface comprises an average surface roughness in the range of 10 angstroms and less.

11. The method of claim 1 further comprising immersing said implanted first substrate in a cleaning solution.

12. The method of claim 11 wherein said cleaning solution comprises an SC1 fluid.

13. The method of claim 11 wherein said cleaning solution comprises an SC2 fluid.

14. The method of claim 13 wherein said SC2 fluid comprises a dilute solution of NH₄OH.

15. The method of claim 14 wherein said dilute solution is about a {fraction (1/500)} part dilution of NH₄OH.

16. The method of claim 1 further comprising plasma cleaning said implanted substantially planar surface.

17. The method of claim 1 further comprising plasma cleaning said face of said second substrate.

18. The method of claim 1 further comprising implanting said face of said second substrate to form a volume of compliant material before said contacting.

20. The method of claim 19 wherein said annealing re-crystallizing a portion of said volume of said amorphous silicon material.

21. The method of claim 19 wherein said implanted substantially planar surface comprises an average surface roughness of 1 angstrom and less.

22. The method of claim 19 wherein said implanted substantially planar surface comprises a plurality of an imperfections, said imperfections comprising a hillock.

19. A method for forming a silicon-on-silicon substrate, said method comprising:

providing a first silicon substrate having a substantially planar surface;

implanting a plurality of particles into said substantially planar surface to a selected depth to define a volume within said substrate, said volume comprising an amorphous silicon material that has a compliant characteristic;

attaching a face of a second silicon substrate against said substantially planar surface to form a multi-layered substrate; and

annealing said multi-layered substrate at a temperature of less than about 200 degrees Celsius to substantially bond said second silicon substrate to said first silicon substrate.

23. A partially completed semiconductor substrate, said substrate comprising:

a substantially planar surface;

a volume of substrate material comprising particles implanted through said substantially planar surface to a selected depth, said volume of substrate material having a compliant characteristic from an amorphous material from said selected depth to said substantially planar surface;

wherein said implanted substantially planar surface comprising an activated surface to be bonded to a second surface;

wherein said compliant characteristic allows a surface imperfection to be embedded into said volume of substrate material when said second surface bonds to said substantially planar surface.