Trench mosfet with structure having low gate charge

• US 20030011028A1
• Filed: 09/13/2002
• Published: 01/16/2003
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: Fwu-Luan Hshieh, Koon Chong So, Yan Man Tsui
• Original Assignee: Fwu-Luan Hshieh, Koon Chong So, Yan Man Tsui
• Inventors: Hshieh, Fwu-luan, So, Koon Chong, Tsui, Yan Man
• Granted Patent: US 6,713,352 B2
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 257/907 Folded bit line dram configuration
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

A trench MOSFET device and method of making the same. The trench MOSFET device comprises:

a) semiconductor substrate of first conductivity type;

b) an epitaxial region of first conductivity type provided within a lower portion of a semiconductor epitaxial layer disposed on the substrate, wherein the epitaxial region of first conductivity type has a lower majority carrier concentration than the substrate;

c) a region of second conductivity type provided within an upper portion of the semiconductor epitaxial layer;

d) a plurality of trench segments in an upper surface of the semiconductor epitaxial layer, wherein: i) the plurality of trench segments extend through the region of second conductivity type and into the epitaxial region of first conductivity type, ii) each trench segment is at least partially separated from an adjacent trench segment by a terminating region of the semiconductor epitaxial layer, and iii) the trench segments define a plurality of polygonal body regions within the region of second conductivity type;

e) a first insulating layer at least partially lining each trench segment;

f) a plurality of first conductive regions within the trench segments adjacent to the first insulating layer, wherein each of the first conductive regions is connected to an adjacent first conductive region by a connecting conductive region that bridges at least one of the terminating regions; and

g) a plurality of source regions of the first conductivity type positioned within upper portions of the polygonal body regions and adjacent the trench segments.

The body regions are preferably either rectangular body regions defined by four trench segments or hexagonal body regions defined by six trench segments.

Claims

1. A trench MOSFET device comprising:

a semiconductor substrate of first conductivity type;

an epitaxial region of first conductivity type provided within a lower portion of a semiconductor epitaxial layer disposed on said substrate, said epitaxial region of first conductivity type having a lower majority carrier concentration than said substrate;

a region of second conductivity type provided within an upper portion of said semiconductor epitaxial layer;

a plurality of trench segments in an upper surface of said semiconductor epitaxial layer, said plurality of trench segments extending through the region of second conductivity type and into said epitaxial region of first conductivity type, each said trench segment being at least partially separated from an adjacent trench segment by a terminating region of said semiconductor epitaxial layer, said trench segments defining a plurality of polygonal body regions within said region of second conductivity type;

a first insulating layer at least partially lining each said trench segment;

a plurality of first conductive regions within said trench segments adjacent to the first insulating layer, each said first conductive regions being connected to an adjacent first conductive region by a connecting conductive region that bridges at least one of said terminating regions; and

a plurality of source regions of said first conductivity type positioned within upper portions of said polygonal body regions and adjacent said trench segments.

2. The trench MOSFET device of claim 1, wherein said plurality of body regions are rectangular body regions defined by four trench segments.

3. The trench MOSFET device of claim 1, wherein a said plurality of body regions are hexagonal body regions defined by six trench segments.

4. The trench MOSFET device of claim 1, wherein said trench MOSFET device is a silicon device.

5. The trench MOSFET device of claim 1, wherein the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity.

6. The trench MOSFET device of claim 1, further comprising a drain electrode disposed on a surface of the substrate and a source electrode disposed on at least a portion of the source regions.

7. The trench MOSFET device of claim 1, wherein said first insulating layer is an oxide layer.

8. The trench MOSFET device of claim 1, wherein said first conductive regions and said connecting conductive regions are polysilicon regions.

9. The trench MOSFET device of claim 5, wherein said substrate is an N+ substrate, said epitaxial region of first conductivity type is an N region, said body regions comprise P regions, and said source regions are N+ regions.

10. A method of forming a trench MOSFET device comprising:

providing semiconductor substrate of first conductivity type;

forming a semiconductor epitaxial layer over said semiconductor substrate, said epitaxial layer being of said first conductivity type and having a lower majority carrier concentration than said substrate;

forming a region of second conductivity type within an upper portion of said semiconductor epitaxial layer, such that an epitaxial region of first conductivity type remains within a lower portion said semiconductor epitaxial layer;

forming a plurality of trench segments in an upper surface of said epitaxial layer, (i) said trench segments extending through the region of second conductivity type and into said epitaxial region of first conductivity type, (ii) each said trench segment being at least partially separated from an adjacent trench segment by a terminating region of said semiconductor epitaxial layer, and (iii) said trench segments defining a plurality of polygonal body regions within said region of second conductivity type;

forming a first insulating layer lining each said trench segment;

forming a plurality of first conductive regions within said trench segments adjacent to the first insulating layer;

forming a plurality of connecting conductive regions, each of said connecting conductive regions bridging at least one of said terminating regions and connecting one of said first conductive regions to an adjacent first conductive region; and

forming a plurality of source regions of said first conductivity type within upper portions of said polygonal body regions and adjacent said trench segments.

11. The method of claim 10, wherein said polygonal body regions are rectangular body regions, each defined by four trench segments.

12. The method of claim 10, wherein a said polygonal body regions are hexagonal body regions, each defined by six trench segments.

13. The method of claim 10, wherein said MOSFET device is a silicon device.

14. The method of claim 10, wherein said step of forming said region of second conductivity type comprising implanting and diffusing a dopant into the epitaxial layer.

15. The method of claim 10, wherein the step of forming said trench segments comprises forming a patterned masking layer over the epitaxial layer and etching said trenches through said masking layer.

16. The method of claim 10, wherein said first insulating layer is an oxide layer.

17. The method of claim 16, wherein the oxide layer is formed via dry oxidation.

18. The method of claim 10, wherein the first conductive regions and the connecting conductive regions are polysilicon regions.

19. The method of claim 18, wherein the plurality of first conductive regions and the plurality of connecting conductive regions are formed simultaneously.

20. The method of claim 19, wherein said plurality of first conductive regions and said plurality of connecting conductive regions are formed by a method comprising depositing a layer of polycrystalline silicon, placing a patterned masking layer over said polycrystalline silicon, and etching the polycrystalline silicon layer though said patterned mask.

21. The method of claim 14, wherein the step of forming the source regions comprises forming a patterned masking layer and implanting and diffusing a dopant into upper portions of the polygonal body regions.

22. The method of claim 16, wherein said first conductivity type is N-type conductivity, and wherein said second conductivity type is P-type conductivity.